Abstract: A method and a circuit for standardizing a noise source providing an initial bit flow, including dividing the initial bit flow into bit words of identical lengths, and assigning an output state according to the states of the bits of the current word and to a pre-established assignment rule, the assignment rule being inverted according to the occurrence, in the initial bit flow, of words, all the bits of which have identical states.

Abstract: A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the initial flow an output state, the occurrence of a word, all the bits of which have identical states, alternately resulting in the assignment of a first state or of a second one.

Abstract: A method for masking several identical functional processes manipulating digital data, including dividing the functional processes into steps at the end of each of which the process can be interrupted with the storage of at least one intermediary result, and successively executing the steps of at least two processes and selecting, at each step end, the process of the next step according to the result of a non-deterministic drawing of a number.

Abstract: A cell for detecting a disturbance capable of affecting the operation of a processor in which it is integrated, including circuitry for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.

Abstract: A method for controlling the execution of a program implementing successive operations, including, during program execution, comparing each operation with a pre-established list, and for each operation contained in the list, incrementing and memorizing a number of occurrences of this operation; and at the end of the program execution, comparing the number of occurrences of the current program execution for each operation with previously-stored ranges of numbers of occurrences assigned to each operation.

Abstract: A device for selecting an operating mode of an integrated circuit, comprising a ROM storing at least one predetermined value formed of data words, a non-volatile programmable memory controllable to store said predetermined value, a comparator indicating how many data words of the value stored in the programmable memory are identical to the data words of the predetermined value, and a control means deactivating a selection signal for selecting the operating mode when the number of identical words is greater than a predetermined threshold.

Abstract: A device for selecting an operating mode of an integrated circuit, including a non-volatile memory programmable after manufacturing exhibiting prior to any programming an initial content, means for storing a first signature representative of the initial content of the memory, means for calculating a second signature representative of a current content of the memory, and means for evaluating a difference between the first and second signatures and for deactivating an operating mode selection signal when the difference is greater than a predetermined threshold.

Abstract: An antifraud method including randomizing the physical signature of an integrated circuit executing a main program, including providing in the main program a branch to a randomly-chosen address of a sub-program having at least the feature that any operation code that it contains directly or indirectly leads to an instruction included in the same sub-program except for at least one instruction for returning to the main program, to randomize the total execution time of the main program.

Abstract: An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least one source register and at least one destination register, respectively, and including means for loading a random number at least in the destination register.

Abstract: A method for controlling the execution of a program implementing, consisting of associating with each operator an initial digital code and a final digital code which are linked to each other by a degradation function applied a number of times depending on the execution of this operator; applying, to the content of a register initialized at each instruction beginning by the initial code of the corresponding operator, said degradation function a number of times depending on the operator execution; and checking, at least at each instruction end, the coherence between the register content and the final code of the corresponding operator.

Abstract: The protected method of cryptographic computation includes N computation rounds successively performed to produce an output data from an input data and a private key. The method also includes a first masking stage to mask the input data, so that each intermediate data used or produced by a computation round is masked, and a second masking stage to mask data manipulated inside each computation round.

Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.

Abstract: A method of cyphering and/or decyphering, by an integrated circuit, of a digital input code by means of several keys, consisting of: dividing said code into several data blocks of same dimensions; and applying to said blocks several turns of a cyphering or decyphering consisting of submitting each block to at least one same non-linear transformation and of subsequently combining each block with a different key at each turn, the operands being masked, upon execution of the method, by means of at least one first random number having the size of said code and all the blocks of which have the same value by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.

Abstract: A method for testing the resistance of an algorithm using at least one secret quantity against attacks measuring physical effects of the execution of the algorithm by an integrated circuit, consisting of implementing statistical key search functions based on hypotheses about at least some bits thereof, by exploiting the input and output values of steps of the algorithm.

Abstract: A method is provided for secured transfer of an N-byte data element from a first memory containing the data element to a second memory through a data bus that is connected between the first memory -and the second memory. According to the method, a transfer rule is defined with at least one parameter whose value is chosen at random before each transfer of the data element. The N-byte data element is transferred byte-by-byte through the data bus in accordance with the transfer rule, with each byte transiting once and only once through the data bus. In a preferred method, the transfer rule is a permutation of the bytes of the N-byte data element. Also provided is a programmable circuit having a random number generator that supplies at least one parameter of a data transfer rule.

Abstract: A method is provided for secured transfer of data from a first memory containing the data element to a second memory through a data bus that is connected between the first memory and the second memory. According to the method, a secret N-byte data element is transferred byte-by-byte through the data bus, with each byte transiting at least once on the data bus. Before each transfer of a byte of the secret data element, a current index ranging from 0 to N−1 is randomly chosen, with the current index corresponding to a place value of the byte to be transferred. At each transfer of a byte of the secret data element with a place value equal to the current index, a corresponding bit of an N-byte loading indicator is modified as a function of a loading mode, with the loading mode being an integer ranging from 0 to a first constant. The transfer of the secret data element is ended when the loading indicator takes a predetermined value.