Patents by Inventor Yantao Ma
Yantao Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798634Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: GrantFiled: February 18, 2022Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Publication number: 20230178141Abstract: A device may include a level shifter including an at least one input and at least one output. The device may also include a logic circuit coupled to an output of the at least one output of the level shifter and configured to receive a power up reset signal. The logic circuit may be configured to isolate an output of the logic circuit from a supply voltage responsive to the power up reset signal and during at least a portion of a power up sequence. Associated circuits, systems, and methods are also disclosed.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Inventors: Hiroshi Akamatsu, Yantao Ma
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Publication number: 20230109187Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: ApplicationFiled: October 5, 2022Publication date: April 6, 2023Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Patent number: 11487346Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: GrantFiled: June 2, 2020Date of Patent: November 1, 2022Assignee: Micron Technogy, Inc.Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Publication number: 20220246219Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: ApplicationFiled: February 18, 2022Publication date: August 4, 2022Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Patent number: 11257549Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: GrantFiled: May 8, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Publication number: 20210373648Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: ApplicationFiled: June 2, 2020Publication date: December 2, 2021Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Publication number: 20210350861Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: ApplicationFiled: May 8, 2020Publication date: November 11, 2021Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Patent number: 11171659Abstract: Techniques for reliable clock speed change and associated circuits and methods are disclosed. Internal voltage supplies of semiconductor devices may include oscillators and charge pump circuits. The oscillator may include at least two clock paths for generating clock signals having different clock frequencies, which can be provided to the charge pump circuit. Further, the oscillator may generate a reset signal configured to activate one clock path over the other (e.g., changing clock speeds). In some embodiments, the oscillator includes a flip-flop to align the reset signal with respect to an edge of an input clock signal supplied to the oscillator such that unintentional (undesired, unexpected) features in the output signal of the oscillator can be avoided when the oscillator changes clock speeds.Type: GrantFiled: January 5, 2021Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Pu Yang, Yantao Ma
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Publication number: 20200277567Abstract: Provided are chemical inducers of lineage reprogramming (CiLR) which include glycogen synthase kinase inhibitors, TGF? receptor inhibitors, cyclic AMP agonists or histone acetylators. Also provided is a method of inducing lineage reprograming in a partially or completely differentiated cell of a first type into a cell with characteristics of a second and different lineage. The method includes: contacting a cell with the CiLR for a sufficient period of time to result in reprograming the cell into a modified XEN-like cell which is subsequently programmed into a cell with characteristics of a second and different lineage.Type: ApplicationFiled: May 31, 2017Publication date: September 3, 2020Inventors: Hongkui Deng, Xiang Li, Defang Liu, Yantao Ma, Xiaomin Du
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Patent number: 10755756Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.Type: GrantFiled: July 10, 2019Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Huy T. Vo
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Publication number: 20190333554Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.Type: ApplicationFiled: July 10, 2019Publication date: October 31, 2019Applicant: Micron Technology, Inc.Inventors: Yantao Ma, Huy T. Vo
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Patent number: 10460777Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.Type: GrantFiled: July 17, 2018Date of Patent: October 29, 2019Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Huy T. Vo
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Patent number: 10439601Abstract: Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.Type: GrantFiled: December 28, 2017Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10431271Abstract: Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation.Type: GrantFiled: September 17, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10312895Abstract: Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.Type: GrantFiled: July 5, 2018Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10312894Abstract: According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal.Type: GrantFiled: September 27, 2018Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10312893Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.Type: GrantFiled: May 24, 2017Date of Patent: June 4, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10305459Abstract: Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: June 14, 2017Date of Patent: May 28, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma
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Patent number: 10284186Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.Type: GrantFiled: September 14, 2017Date of Patent: May 7, 2019Assignee: Micron Technology, Inc.Inventor: Yantao Ma