Abstract: Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

Abstract: Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.

Abstract: Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.

Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.

Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.

Abstract: Apparatuses, methods, and duty cycle correction circuits are described. An example apparatus includes a duty cycle correction (DCC) adjustment circuit configured to receive an input signal, and to adjust a duty cycle of the input signal to provide an output signal. The DCC circuit including a coarse adjust control circuit configured to adjust the duty cycle of the input signal by a first amount that is equal to one or more unit adjustments, and a fine adjust control circuit that is configured to adjust the duty cycle of the input signal responsive to a pulse signal by a second amount that is less than the unit adjustment.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be coupled to a node between two adjacent gates of the plurality of gates and controlled responsive to a first control signal. A second pull-down circuit can be coupled to an output of one of the gates and controlled responsive to a second control signal. A duty cycle of a signal provided by the plurality of gates can be increased responsive to the first control signal and can be decreased responsive to the second control signal. The plurality of gates and the first and second pull-down circuits can make up a duty cycle adjuster circuit that can adjust the duty cycle of the signal by adjusting only a single type of edges of the signal.

Abstract: Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.

Abstract: An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be coupled to a node between two adjacent gates of the plurality of gates and controlled responsive to a first control signal. A second pull-down circuit can be coupled to an output of one of the gates and controlled responsive to a second control signal. A duty cycle of a signal provided by the plurality of gates can be increased responsive to the first control signal and can be decreased responsive to the second control signal. The plurality of gates and the first and second pull-down circuits can make up a duty cycle adjuster circuit that can adjust the duty cycle of the signal by adjusting only a single type of edges of the signal.

Abstract: Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example apparatus includes a signal path and signal path delay compensation circuit. The signal path includes a plurality of signal driver circuits coupled in series. The signal path delay compensation circuit includes an adjustable path delay circuit and a bias circuit. The adjustable path delay circuit is coupled to an output of a signal driver circuit of the plurality of signal driver circuits and includes a latch circuit. The bias circuit is configured to change a resistance to switching a latched signal level of the latch circuit responsive to changes in power provided to the signal path. Additional example apparatuses and methods are also disclosed.

Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be coupled to a node between two adjacent gates of the plurality of gates and controlled responsive to a first control signal. A second pull-down circuit can be coupled to an output of one of the gates and controlled responsive to a second control signal. A duty cycle of a signal provided by the plurality of gates can be increased responsive to the first control signal and can be decreased responsive to the second control signal. The plurality of gates and the first and second pull-down circuits can make up a duty cycle adjuster circuit that can adjust the duty cycle of the signal by adjusting only a single type of edges of the signal.

Abstract: Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster circuit. The phase mixer may have a first step duty cycle response and may be configured to provide a first output signal to the node in accordance with the first step duty cycle response. The duty cycle adjuster circuit may have a second step duty cycle response complementary to the first step duty cycle response and may be configured to provide a second signal to the node in accordance with the second step duty cycle response.

Abstract: Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example apparatus includes a signal path and signal path delay compensation circuit. The signal path includes a plurality of signal driver circuits coupled in series. The signal path delay compensation circuit includes an adjustable path delay circuit and a bias circuit. The adjustable path delay circuit is coupled to an output of a signal driver circuit of the plurality of signal driver circuits and includes a latch circuit. The bias circuit is configured to change a resistance to switching a latched signal level of the latch circuit responsive to changes in power provided to the signal path. Additional example apparatuses and methods are also disclosed.

Abstract: Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal.