Patents by Inventor Yao-An Chung

Yao-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099199
    Abstract: A garden shears has an anvil portion, a driving arm, a blade portion and a plurality of pivot shafts. The anvil portion sandwiched an anvil, and the anvil portion and the driving arm are pivoted together by a pivot shaft. A gear and the blade portion are disposed between the driving arm. The blade portion has a straight groove and a rack portion. A pivot shaft is used to pivot the gear and the driving together is engaged and another pivot shaft passes through the straight groove and the driving arm with the pivot shaft capable of sliding in the straight groove and the gear being engaged with the rack portion to achieve the effect of a stable speed.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventor: Yao-Chung Huang
  • Patent number: 11908905
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: 11906355
    Abstract: An in-cell optical sensing display panel includes a pixel array, a plurality of first optical sensors and a plurality of second optical sensors. The pixel array is disposed in an active area of the in-cell optical sensing display panel, and the active area includes a first region and a second region which surrounds the first region. The sensor array is disposed in the first region of the active area and is configured to sense a fingerprint of a finger touching a surface of the in-cell optical sensing display panel. The second optical sensors are disposed in the second region of the active area and are configured to sense ambient light, and the second optical sensors are not to be used for fingerprint sensing.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 20, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yu-Ying Tang, Yao Chung Chang, Chih-Chang Lai
  • Publication number: 20240053280
    Abstract: Methods and systems for compensating systematic errors across a fleet of metrology systems based on a trained error evaluation model to improve matching of measurement results across the fleet are described herein. In one aspect, the error evaluation model is a machine learning based model trained based on a set of composite measurement matching signals. Composite measurement matching signals are generated based on measurement signals generated by each target measurement system and corresponding model-based measurement signals associated with each target measurement system and reference measurement system. The training data set also includes an indication of whether each target system is operating within specification, an indication of the values of system model parameter of each target system, or both.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 15, 2024
    Inventors: Ming Di, Yih-Chung Chang, Xi Chen, Dawei Hu, Ce Xu, Bowei Huang, Igor Baskin, Mark Allen Neil, Tianhao Zhang, Malik Karman Sadiq, Shankar Krishnan, Jenching Tsai, Carlos L. Ygartua, Yao-Chung Tsao, Qiang Zhao
  • Publication number: 20240039815
    Abstract: An example method for using wireless packets to indicate boot status of a network device is disclosed. The method includes initiating a boot sequence of a network device. The method also includes during at least a portion of the boot sequence, transmitting a first wireless packet comprising data indicating a boot status of the network device, wherein the boot status indicates the network device is booting. The method also includes transmitting a second wireless packet comprising data indicating the boot status of the network device, wherein the boot status indicates the network device has finished booting.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventors: Robert J. Pera, Yao-Chung Chang, Andrejs Bogdanovs
  • Patent number: 11870833
    Abstract: Methods and systems for encoder parameter setting optimization. A media item to be provided to one or more users of a platform is identified. The media item is associated with a media class. An indication of the identified media item is provided as input to a first machine learning model. The first machine learning model is trained to predict, for a given media item, a set of encoder parameter settings that satisfy a performance criterion in view of a respective media class associated with the given media item. One or more outputs of the first machine learning model are obtained. The one or more obtained outputs include encoder data identifying one or more sets of encoder parameter settings and, for each of the sets of encoder parameter settings, an indication of a level of confidence that a respective set of encoder parameter settings satisfies the performance criterion in view of the media class associated with the identified media item.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Google LLC
    Inventors: Ching Yin Derek Pang, Kyrah Felder, Akshay Gadde, Paul Wilkins, Cheng Chen, Yao-Chung Lin
  • Patent number: 11859393
    Abstract: A raised floor system for suspension type pipelines mainly comprises girders and floor units laid between foot stands after the foot stands are erected at intervals on the floor, such that floor units are separated from the floor by a distance to form a large-area raised floor, wherein a top portion of each foot stand for the floor units to be placed thereon is combined with a cover, of four sides of the cover each is vertically provided with a folded plate, a hole is formed on the folded plate, two ends of a suspension device are capable of being respectively hooked on the holes of the folded plates of two of the spaced foot stands, so that the suspension device is placed under the floor units for pipelines to be placed thereon or fixed thereto.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 2, 2024
    Inventors: Yao-Chung Chen, Shih-Jan Wang
  • Publication number: 20230413503
    Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.
    Type: Application
    Filed: August 7, 2023
    Publication date: December 21, 2023
    Inventors: Shau-Wei LU, Hao Chang, Kun-Hsi Li, Kuo-Hung Lo, Kang-Yu Hsu, Yao-Chung Hu
  • Patent number: 11832429
    Abstract: A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shau-Wei Lu, Hao Chang, Kun-Hsi Li, Kuo-Hung Lo, Kang-Yu Hsu, Yao-Chung Hu
  • Publication number: 20230326890
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 12, 2023
    Inventors: Yao-Chung Chang, Shih-Chien Liu, Chia-Jui Yu, Chun-Lin Tsai
  • Patent number: 11784900
    Abstract: An example method for using wireless packets to indicate boot status of a network device is disclosed. The method includes initiating a boot sequence of a network device. The method also includes during at least a portion of the boot sequence, transmitting a first wireless packet comprising data indicating a boot status of the network device, wherein the boot status indicates the network device is booting. The method also includes transmitting a second wireless packet comprising data indicating the boot status of the network device, wherein the boot status indicates the network device has finished booting.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: October 10, 2023
    Assignee: Ubiquiti Inc.
    Inventors: Robert J. Pera, Yao-Chung Chang, Andrejs Bogdanovs
  • Publication number: 20230123907
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: YAO-CHUNG CHANG, PO-CHIH CHEN, JIUN-LEI JERRY YU, CHUN LIN TSAI
  • Publication number: 20230120292
    Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.
    Type: Application
    Filed: February 15, 2022
    Publication date: April 20, 2023
    Inventors: Shih-Pang Chang, Haw-Yun Wu, Yao-Chung Chang, Chun-Lin Tsai
  • Patent number: 11629706
    Abstract: A vacuum cathode arc-induced pulsed thruster includes a housing where a triggering room and an electric discharging room are defined and are in communication with each other, a first anode unit and a first cathode unit concentrically disposed in the triggering room, a second anode unit disposed in the electric discharging room, an insulating fuel layer concentrically located between the first anode unit and the first cathode unit, a main insulating layer concentrically surrounded by the first cathode unit, and a second cathode unit inserted from the triggering room into the electric discharging room. Thus, the vacuum cathode arc-induced pulse thruster is lightweight and has low manufacturing costs, low system complexity, and less energy consumption. Carbon deposition caused during an electric discharging process is prevented from affecting an inducing effect to thereby prolong the service life of the thruster and increase the control precision and inducing precision effectively.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: April 18, 2023
    Assignees: National Cheng Kung University, Taiwan Space Agency
    Inventors: Yueh-Heng Li, Sheng-Wen Liu, Hou-Yi Lee, Tien-Chuan Kuo, Yao-Chung Hsu
  • Publication number: 20230104190
    Abstract: An image sensor includes: a plurality of sensing portions; a color filter layer disposed on the sensing portions; and a micro-lens disposed on the color filter layer. The micro-lens includes a positive radius of curvature, and a dish structure including a negative radius of curvature is formed within the micro-lens.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Inventors: Yao-Chung TUNG, Zong-Ru TU, Chi-Han LIN
  • Publication number: 20230071860
    Abstract: A raised floor system for suspension type pipelines mainly comprises girders and floor units laid between foot stands after the foot stands are erected at intervals on the floor, such that floor units are separated from the floor by a distance to form a large-area raised floor, wherein a top portion of each foot stand for the floor units to be placed thereon is combined with a cover, of four sides of the cover each is vertically provided with a folded plate, a hole is formed on the folded plate, two ends of a suspension device are capable of being respectively hooked on the holes of the folded plates of two of the spaced foot stands, so that the suspension device is placed under the floor units for pipelines to be placed thereon or fixed thereto.
    Type: Application
    Filed: October 12, 2021
    Publication date: March 9, 2023
    Inventors: Yao-Chung CHEN, Shih-Jan WANG
  • Publication number: 20230068026
    Abstract: Methods and systems for encoder parameter setting optimization. A media item to be provided to one or more users of a platform is identified. The media item is associated with a media class. An indication of the identified media item is provided as input to a first machine learning model. The first machine learning model is trained to predict, for a given media item, a set of encoder parameter settings that satisfy a performance criterion in view of a respective media class associated with the given media item. One or more outputs of the first machine learning model are obtained. The one or more obtained outputs include encoder data identifying one or more sets of encoder parameter settings and, for each of the sets of encoder parameter settings, an indication of a level of confidence that a respective set of encoder parameter settings satisfies the performance criterion in view of the media class associated with the identified media item.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Ching Yin Derek Pang, Kyrah Felder, Akshay Gadde, Paul Wilkins, Cheng Chen, Yao-Chung Lin
  • Publication number: 20230019983
    Abstract: A vacuum cathode arc-induced pulsed thruster includes a housing where a triggering room and an electric discharging room are defined and are in communication with each other, a first anode unit and a first cathode unit concentrically disposed in the triggering room, a second anode unit disposed in the electric discharging room, an insulating fuel layer concentrically located between the first anode unit and the first cathode unit, a main insulating layer concentrically surrounded by the first cathode unit, and a second cathode unit inserted from the triggering room into the electric discharging room. Thus, the vacuum cathode arc-induced pulse thruster is lightweight and has low manufacturing costs, low system complexity, and less energy consumption. Carbon deposition caused during an electric discharging process is prevented from affecting an inducing effect to thereby prolong the service life of the thruster and increase the control precision and inducing precision effectively.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 19, 2023
    Inventors: YUEH-HENG LI, SHENG-WEN LIU, HOU-YI LEE, TIEN-CHUAN KUO, YAO-CHUNG HSU
  • Patent number: 11532740
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Publication number: 20220352325
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang