Patents by Inventor Yao-An Tsai

Yao-An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240084028
    Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 14, 2024
    Inventors: Rong-Hwa LIN, Shih-Yao LIN, Yu-Ying TSAI
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Patent number: 11923870
    Abstract: A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n?k of independent spinors Sr from the first stabilizer C and a first ordered set SC consists of the independent spinors Sr; choosing a number n?k of independent spinors ?r from a second stabilizer ? in the intrinsic coordinate and a second ordered set ?r consists of the independent spinors ?r consist; implementing an encoding Qen, wherein the encoding Qen converts the first ordered set SC to the second ordered set S?, wherein the encoding Qen is a sequential product provided by sequential operations of a number n?k of unitary operators Qr; wherein each of the unitary operator Qr is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Qen converts and maps the rth independent spinor Sr in the first ordered set SC to the rth independent spinor ?r in the second ordered set S? correspondingly; a fault tolerant action Û i
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 5, 2024
    Assignee: National Applied Research Laboratories
    Inventors: Zheng-Yao Su, Ming-Chung Tsai
  • Publication number: 20240071909
    Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen WU, Techi WONG, Po-Hao TSAI, Po-Yao CHUANG, Shih-Ting HUNG, Shin-Puu JENG
  • Publication number: 20240053758
    Abstract: A self-moving robot and a method of automatically determining an accessible region are provided. The self-moving robot performs a setting process of 2D obstacles to generate a goal map based on an exploration map, performs a setting process of 3D obstacles on the goal map to update the accessible region of the goal map when a 3D obstacle is detected, performs an avoidance action, and, moves within the accessible region of the goal map. The disclosure prevents the self-moving robot from colliding with obstacles or being trapped.
    Type: Application
    Filed: December 9, 2022
    Publication date: February 15, 2024
    Inventors: Huan-Chen LING, Tien-Ping LIU, Chung-Yao TSAI
  • Publication number: 20230388243
    Abstract: A first communication device for handling a real-time data transmission includes an identification module for identifying at least one first real-time data, and for storing at least one first arrival time of the at least one first real-time data; a prediction module for predicting a second arrival time of a second real-time data according to the at least one first arrival time and a prediction algorithm in order to generate a first prediction result; a scheduling module for scheduling the second real-time data according to the first prediction result to generate a first scheduling result; a reservation module for reserving a transmission resource according to the first scheduling result; and a transmission module for transmitting the second real-time data according to the first scheduling result via the transmission resource.
    Type: Application
    Filed: August 16, 2022
    Publication date: November 30, 2023
    Applicant: Moxa Inc.
    Inventors: Chang-Mou Yang, Hsu-Yao Tsai
  • Patent number: 11759799
    Abstract: A shower head includes a housing, and a jet faceplate mounted to the housing and including a first water jetting area composed of a plurality of subunits and a second water jetting area having a second jet hole therein. The subunits are arranged to present an arc-shaped distribution, each defining therein a plurality of first jet holes. The subunits are in a fan-shaped area of the jet faceplate so that the water line of the ejected water can be concentrated and fan-shaped, enhancing the effect of removing dirt.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 19, 2023
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Chun-Hung Li, Hui-Ling Chiu, Tun-Yao Tsai
  • Patent number: 11513287
    Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Chien Shih Tsai, Shih-Che Hung
  • Publication number: 20220289564
    Abstract: A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
  • Patent number: 11345591
    Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
  • Publication number: 20210224822
    Abstract: In an intelligent electronic atomization system with an authentication anti-counterfeiting mechanism, a wireless communication module of a main body of an intelligent electronic atomization device is connected to a smart handheld device of a user before being used, so that authentication of user identification can be performed through the smart handheld device and a cloud server. After an atomizing member has been combined with the main body, the main body and the atomizing member perform mutual interpretation operations in every series of inhaling and exhaling actions. After a protocol has been interpreted as correct, the atomizing member sends a dynamic password to the main body to perform interpretation. The main body immediately wakes up the atomizing member after the main body has interpreted the dynamic password as correct. Finally, the main body transmits a driving current to the atomizing member.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Yao-An Tsai, Hao-Yang Tsai
  • Patent number: 11062903
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Neena Avinash Gilda, Lien-Yao Tsai, Baohua Niu
  • Patent number: 10981779
    Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
  • Patent number: 10915963
    Abstract: An investment strategy rule generation method including the following steps is provided. Firstly, an investment strategy rule generator generates an investment strategy model according to an investment history trend. Then, a total investment return of each of N candidate investment rules is obtained by the investment strategy rule calculator, wherein each of the N candidate investment rules includes a candidate market direction rule. The obtaining step includes: performing an investment simulation in each of multiple time points in a time window of a time interval. Then, the total investment return under the operation of the investment simulations over the time interval is calculated by the investment strategy rule calculator. Then, the candidate investment rule corresponding to the best of the total investment returns is used as an investment strategy rule of the investment strategy model by the investment strategy rule calculator.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 9, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: En-Tzu Wang, Chi-Yuan Yeh, Sian-Hong Huang, Ming-Yao Tsai
  • Patent number: 10865100
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
  • Patent number: 10861929
    Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Baohua Niu, Yi-Chuan Teng, Chi-Yuan Shih
  • Patent number: D963121
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: September 6, 2022
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventor: Tun-Yao Tsai
  • Patent number: D986383
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Globe Union Industrial Corp.
    Inventor: Tun-Yao Tsai
  • Patent number: D1016226
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: February 27, 2024
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventor: Tun-Yao Tsai
  • Patent number: D1018527
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 19, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Tsai Liu, Jyh-Chyang Tzou, Cheng-Shiue Jan, Yao-Hsien Yang, Pai-Feng Chen, I-Hao Chen