Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A voltage is applied to the intermediate layer. A unit cell of the intermediate layer is stretched or compressed by the voltage. The polarity of the intermediate layer is changed by the voltage.

Abstract: A shower head includes a housing, and a jet faceplate mounted to the housing and including a first water jetting area composed of a plurality of subunits and a second water jetting area having a second jet hole therein. The subunits are arranged to present an arc-shaped distribution, each defining therein a plurality of first jet holes. The subunits are in a fan-shaped area of the jet faceplate so that the water line of the ejected water can be concentrated and fan-shaped, enhancing the effect of removing dirt.

Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A voltage is applied to the intermediate layer. A unit cell of the intermediate layer is stretched or compressed by the voltage. The polarity of the intermediate layer is changed by the voltage.

Abstract: An investment strategy rule generation method including the following steps is provided. Firstly, an investment strategy rule generator generates an investment strategy model according to an investment history trend. Then, a total investment return of each of N candidate investment rules is obtained by the investment strategy rule calculator, wherein each of the N candidate investment rules includes a candidate market direction rule. The obtaining step includes: performing an investment simulation in each of multiple time points in a time window of a time interval. Then, the total investment return under the operation of the investment simulations over the time interval is calculated by the investment strategy rule calculator. Then, the candidate investment rule corresponding to the best of the total investment returns is used as an investment strategy rule of the investment strategy model by the investment strategy rule calculator.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.

Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The MEMS device structure includes a micro-electro-mechanical system (MEMS) substrate, and a substrate formed over the MEMS substrate. The substrate includes a semiconductor via through the substrate. The MEMS device structure includes a dielectric layer formed over the substrate and a polymer layer formed on the dielectric layer. The MEMS device structure also includes a conductive layer formed in the dielectric layer and the polymer layer. The conductive layer is electrically connected to the semiconductor via, and the polymer layer is between the conductive layer and the dielectric layer.

Abstract: A shower head includes a housing, and a jet faceplate mounted to the housing and including a first water jetting area composed of a plurality of subunits and a second water jetting area having a second aperture therein. The subunits are arranged to present an arc-shaped distribution, each defining therein a plurality of first apertures. The subunits are in a fan-shaped area of the jet faceplate so that the water line of the ejected water can be concentrated and fan-shaped, enhancing the effect of removing dirt.

Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also includes a cap bonded to the first substrate, where the cap and the first substrate define a first sealed cavity and a second sealed cavity. The first conductive feature and the first movable element are disposed in the first sealed cavity and the second conductive feature and the second movable element are disposed in the second sealed cavity. A pressure of the second cavity is higher than a pressure of the first sealed cavity, and an out gas layer is disposed in a recess of the cap that partially defines the second sealed cavity.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

Abstract: An integrated circuit includes a first power unit, a second power unit, and a selection switch. The first power unit generates a first output voltage and is coupled to a first load pin. The first load pin is coupled to a first load. The second power unit generates a second output voltage and is coupled to a second load pin. The second load pin is coupled to a second load. The selection switch outputs either the first output voltage or the second output voltage to a voltage pin according to a selection signal.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The MEMS device structure includes a micro-electro-mechanical system (MEMS) substrate, and a substrate formed over the MEMS substrate. The substrate includes a semiconductor via through the substrate. The MEMS device structure includes a dielectric layer formed over the substrate and a polymer layer formed on the dielectric layer. The MEMS device structure also includes a conductive layer formed in the dielectric layer and the polymer layer. The conductive layer is electrically connected to the semiconductor via, and the polymer layer is between the conductive layer and the dielectric layer.