Patents by Inventor Yao Chen

Yao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243048
    Abstract: An electronic package is provided, in which one of insulating layers inside a package substrate is made of an Ajinomoto build-up film (ABF) material to facilitate the production of circuit structures using a redistribution layer (RDL) process, so that a circuit layer can meet the needs of high-density fine lines/fine spacing.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Andrew C. Chang, Min-Yao Chen, Yin-Ju Chen
  • Publication number: 20240243011
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Application
    Filed: February 26, 2024
    Publication date: July 18, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20240242656
    Abstract: A power supply circuit, a driving method thereof, a printed circuit board, a display module and a display apparatus are disclosed, which relates to a technical field of displaying. The power supply circuit includes a first power management chip and a second power management chip configured to be respectively connected with a display panel and provide different driving signals to the display panel, and the driving signals are configured for driving the display panel to display.
    Type: Application
    Filed: May 20, 2022
    Publication date: July 18, 2024
    Applicants: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Ying Zhang, Jin Sha, Can Shen, Xiang Fang, Bo Ran, Chao Gao, Yao Chen, Yiming Cheng, Jinxiang Li, Shifei Huang, Shengjie Yin, Pan Chen, Jun Tao, Wendi Zhang, Zhou Zhang, Qiuju Xie, Jun Wei, Hongchao Su
  • Publication number: 20240243180
    Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: I-Chen Yang, Chun Liang Lu, Yung-Hsiang Chen, Yao-Wen Chang
  • Patent number: 12040396
    Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Patent number: 12040359
    Abstract: A semiconductor device includes a plurality of channel layers vertically spaced from one another. The semiconductor device includes a gate structure wrapping around each of the plurality of channel layers. The semiconductor device includes an epitaxial structure electrically coupled to the plurality of channel layers. The epitaxial structure contacts a sidewall, a portion of a top surface, and a portion of a bottom surface of each of the plurality of channel layers.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Chao-Cheng Chen
  • Patent number: 12038771
    Abstract: A pressure regulator has a valve tube assembly, a gas-input assembly, a first regulating assembly and a second regulating assembly. The gas storage device has a storage unit and the pressure regulator. By the first and the second regulating assemblies, the effect of adjusting down the gas pressure is achieved to maintain the safety of use. The pressure regulator is partially embedded in the gas storage unit to reduce the overall volume of the gas storage device. However, the high-pressure piston chamber of the valve tube assembly communicates with the outside of the gas storage unit through the high-pressure gas channel to maintain the normal operation of the elastic element in the high-pressure piston chamber.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: July 16, 2024
    Assignee: BANZA STAMPING INDUSTRY CORP.
    Inventors: Li-Wei Chen, Shen-Kai Ho, Tsang-Yao Lu
  • Patent number: 12028000
    Abstract: Disclosed is an object table for holding an object, comprising: an electrostatic clamp arranged to clamp the object on the object table; a neutralizer arranged to neutralize a residual charge of the electrostatic clamp; a control unit arranged to control the neutralizer, wherein the residual charge is an electrostatic charge present on the electrostatic clamp when no voltage is applied to the electrostatic clamp.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: July 2, 2024
    Assignee: ASML Netherlands B.V.
    Inventors: Jan-Gerard Cornelis Van Der Toorn, Jeroen Gertruda Antonius Huinck, Han Willem Hendrik Severt, Allard Eelco Kooiker, Michael Johannes Christiaan Ronde, Arno Maria Wellink, Shibing Liu, Ying Luo, Yixiang Wang, Chia-Yao Chen, Bohang Zhu, Jurgen Van Soest
  • Publication number: 20240215200
    Abstract: The invention provides a heat dissipation module and an electronic device. The heat dissipation module includes a thermally conductive plastic member and a metal member. The thermally conductive plastic member includes a base and a plurality of heat dissipation fins. The base includes an upper surface and a lower surface opposite to each other, and the heat dissipation fins are arranged at intervals at the upper surface. The metal member is disposed at the lower surface of the base. The thermally conductive plastic member and the metal member are combined via insert molding. One of the thermally conductive plastic member and the metal member includes a plurality of heat dissipation bosses separated from each other, and the heat dissipation bosses are located at the lower surface of the base of the thermally conductive plastic member or at a surface of the metal member relatively far away from the base.
    Type: Application
    Filed: December 25, 2023
    Publication date: June 27, 2024
    Applicant: Sercomm Corporation
    Inventors: ChengPu Wu, Sheng-Yao Chen, Yi Fei Yu
  • Publication number: 20240213137
    Abstract: A package substrate is provided, in which a first circuit structure is formed on a core board body, and a second circuit structure is formed on the first circuit structure. A second insulating layer of the second circuit structure is made of an ABF material that is different from a material forming a first insulating layer of the first circuit structure, so that a second circuit layer with fine lines/spaces can be formed by the ABF material of the second insulating layer to achieve a purpose of multi-layer fine lines.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 27, 2024
    Inventors: Andrew C. Chang, Min-Yao Chen, Yin-Ju Chen
  • Patent number: 12016341
    Abstract: A pearl dorayaki structure includes a first internal layer formed of one or multiple pearls in a spherical form, a second internal layer formed of a sticky filling, and surface layers formed of patty in a soft and dense form and wrapping the second internal layer. The surface layers formed by subjecting the dorayaki patty raw material to steps of stirring and heating to be then shaped to form the dorayaki patty; the first internal layer is formed by subjecting the pearl raw material to steps of stirring and steaming so as to be shaped as the pearls; and the second internal layer is formed of the filling that is formed by subjecting fructose and edible shortening to stirring; and the second internal layer and the first internal layer are subjected to stuffing and shaping so as to be wrapped with the surface layers to thereby form the pearl dorayaki.
    Type: Grant
    Filed: December 14, 2023
    Date of Patent: June 25, 2024
    Assignee: SAN SHU GONG FOOD CO., LTD.
    Inventor: Mei-Yao Chen
  • Patent number: 12016348
    Abstract: A method for manufacturing the pearl daifuku characterized in that the surface layer is formed by subjecting the mochi skin raw material to steps of stirring and steaming to be then shaped to form the mochi skin; the first internal layer is formed by subjecting the pearl raw material to steps of stirring and steaming so as to be shaped into the pearls; and the second internal layer and the first internal layer are subjected to stuffing and shaping so as to be wrapped with the surface layer to thereby form the pearl daifuku.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: June 25, 2024
    Assignee: SAN SHU GONG FOOD CO. , LTD.
    Inventor: Mei-Yao Chen
  • Patent number: 12020989
    Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Yao Chen, Chang-Yun Chang, Ming-Chang Wen
  • Publication number: 20240191749
    Abstract: A slide rail device is adapted for collecting drill dust, and includes a fixed rail and a plurality of dust-collecting units. The fixed rail has a first surface and a second surface that are spaced apart from each other, a plurality of through holes that are formed through the first surface and the second surface, and a plurality of through-hole surfaces that respectively define the through holes. Each of the through-hole surfaces defines two openings that are respectively in the first surface and the second surface. Each of the dust-collecting units includes a cover member that closes one of the openings of a respective one of the through-hole surfaces, and a dust-catching member that is adapted for the drill dust to adhere thereto. The cover member of each of the dust-collecting units cooperates with the respective one of the through-hole surfaces to define a dust-collecting space.
    Type: Application
    Filed: October 2, 2023
    Publication date: June 13, 2024
    Inventor: Tsung-Yao CHEN
  • Patent number: 12009266
    Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Yao Chen, Chang-Yun Chang, Ming-Chang Wen
  • Patent number: 12008831
    Abstract: A sensing device substrate includes a substrate and a sensing device. The sensing device is disposed on the substrate and includes a first electrode, a second electrode, a sensing layer, a conductive layer, and a first insulating layer. The first electrode is located on the substrate. The second electrode is overlapped with the first electrode. The sensing layer is located between the second electrode and the first electrode. The conductive layer is overlapped with the second electrode and electrically connected to the first electrode. The conductive layer has a first opening, and the first opening is overlapped with the sensing layer. The first insulating layer is located between the conductive layer and the second electrode. A display apparatus including the sensing device substrate is also provided.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: June 11, 2024
    Assignee: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Jui-Chi Lo, Wei-Ming Huang
  • Patent number: 11997798
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 28, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
  • Publication number: 20240170070
    Abstract: A memory includes at least a target word line and a first word line group and a second word line group respectively stacked on both sides of the target word line. The first word line group includes first word lines, and the second word line group includes second word lines. A method for operating the memory includes, during a pre-charge operation, applying a first bias voltage signal to the plurality of first word lines, applying a second bias voltage signal to a target word line, and applying a third bias voltage signal to the plurality of second word lines. The method also includes, during a programming operation, applying a program voltage signal to a target word line.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 23, 2024
    Inventors: Lu Qiu, Xueqing Huang, Junyao Zhu, Yao Chen
  • Publication number: 20240145581
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20240140452
    Abstract: A controller may generate a packet, and send the packet to an electronic control unit. The packet includes a plurality of bits and control information. The plurality of bits may indicate whether the electronic control unit controls a plurality of objects (for example, actuators or functions) based on the control information. The plurality of bits are in a one-to-one correspondence with the plurality of objects. In this way, the electronic control unit associated with the plurality of objects can control the plurality of objects based on the control information.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Tao MA, Yao CHEN