Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

Abstract: A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

Abstract: A compensation module, an oscillation circuit and associated compensation method for reducing an oscillation frequency variation in an output oscillation signal of a voltage-controlled oscillator (VCO) core are provided. The compensation module includes a compensation circuit and a polarity selection circuit. The compensation circuit has a capacitance value related to voltages of a first and a second receiving terminals. The oscillation frequency variation is changed with the capacitance value. The polarity selection circuit conducts a periodic regulated signal to one of the first receiving terminal and the second receiving terminal. The polarity selection circuit conducts a filtered bias signal to the other of the first receiving terminal and the second receiving terminal. The periodic regulated signal is sensitive to a regulated voltage variation, and the filtered bias signal is insensitive to the regulated voltage variation.

Abstract: A compensation module, an oscillation circuit and associated compensation method for reducing an oscillation frequency variation in an output oscillation signal of a voltage-controlled oscillator (VCO) core are provided. The compensation module includes a compensation circuit and a polarity selection circuit. The compensation circuit has a capacitance value related to voltages of a first and a second receiving terminals. The oscillation frequency variation is changed with the capacitance value. The polarity selection circuit conducts a periodic regulated signal to one of the first receiving terminal and the second receiving terminal. The polarity selection circuit conducts a filtered bias signal to the other of the first receiving terminal and the second receiving terminal. The periodic regulated signal is sensitive to a regulated voltage variation, and the filtered bias signal is insensitive to the regulated voltage variation.

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract: A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

Abstract: A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

Abstract: A circuit system includes a current supply module, a voltage supply module and a voltage-controlled oscillator (VCO). The current supply module provides a current adapted to an ambient temperature. The voltage supply module receives the current and generates an adapted voltage according to the current. The VCO receives the adapted voltage and generates an oscillation signal according to the adapted voltage.

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

Abstract: A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.