Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: A method of generating a layout design of an integrated circuit. The method includes forming a first region having at least two first-type cell rows extending in a first direction. Each one of the first-type cell rows has a first row height measured along a second direction perpendicular to the first direction. The method also includes forming a second region having at least two second-type cell rows extending in the first direction. Each one of the second-type cell rows has a second row height measured along the second direction. The first region is adjacent to the second region, and the first row height of the first-type cell rows is different from the second row height of the second-type cell rows.

Abstract: A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.

Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell in the first circuit; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.

Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.

Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing an electromigration information of the first circuit to determine if the first via pillar induces EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.

Abstract: Exemplary embodiments for various via pillar structures include one or more first conductors in a first interconnect layer of a semiconductor stack interconnected with one or more second conductors in a second interconnect layer of the semiconductor stack. The one or more first conductors and/or the one or more second conductors within the first interconnect layer and the second interconnect layer, respectively, can traverse multiple directions. In some situations, this allows multiple interconnections to be utilized to interconnect the one or more first conductors and the one or more second conductors. These multiple interconnections can reduce resistance between the one or more first conductors and the one or more second conductors thereby improving performance of signals flowing between the one or more first conductors and the one or more second conductors.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.

Abstract: A multi-load fuse block, which receives insertion of at least two safety fuses therein, includes: a housing, a first surface of the housing configured with a first fuse slot and at least one second fuse slot; a conductive joint, configured on a second surface of the housing, and in electric connection with the first fuse slot; a first load conductive wire, configured on a third surface of the housing; and a second load conductive wire, configured on a fourth surface of the housing, where the first fuse slot and second fuse slot allow a plurality of safety fuses to be inserted therein or separated therefrom. The first load conductive wires and second load conductive wires of the housing can provide electric connection for automotive electronics, allowing the safety fuses to be in electric connection with more automotive electronics so as to protect them from overcurrent.

Abstract: A multi-load fuse block, which receives insertion of at least two safety fuses therein, includes: a housing, a first surface of the housing configured with a first fuse slot and at least one second fuse slot; a conductive joint, configured on a second surface of the housing, and in electric connection with the first fuse slot; a first load conductive wire, configured on a third surface of the housing; and a second load conductive wire, configured on a fourth surface of the housing, where the first fuse slot and second fuse slot allow a plurality of safety fuses to be inserted therein or separated therefrom. The first load conductive wires and second load conductive wires of the housing can provide electric connection for automotive electronics, allowing the safety fuses to be in electric connection with more automotive electronics so as to protect them from overcurrent.

Abstract: The fuse box may accommodate at least two fuses, and includes a casing having a first face, a second face, and a third face; a first fuse socket and at least a second fuse socket configured on the first face, where each first and second fuse socket has a first fuse slot and a second fuse slot; a power plug configured on the second face, and electrically connected to the first fuse socket; at least a load cable connected to the third face, where the load cable includes a positive wire and a load wire electrically connecting the first and second fuse slots of the second fuse socket, respectively. The first and second fuse sockets are for the detachable installation of the fuses. As such, two or more fuses may be configured on a single casing to achieve more thorough protection to multiple car appliances.

Abstract: An extended protection device for a vehicle includes: a housing, three conductive wires configured therein, the three conductive wires respectively being a first conductive wire, second conductive wire and third conductive wire extended outward form one end of the housing, another end of the housing configured with a fuse slot, and a combination portion configured on the outside of the fuse slot; a protection element, constituted by two sets of safety fuses, and in corresponding combination with the fuse slot, allowing the protection element to be in electric connection with the first conductive wire, second conduction wire and third conductive wire; and a cover, covered correspondingly on the combination portion of the housing for the protection of the protection element.