Abstract: Phase shifting generates features in a printed features layer, such as a printed circuit, that are narrower than the features on a fabrication layout, such as a mask, projected onto the printed features layer using the same optical system without phase shifting. Techniques for forming a fabrication layout for a physical design layout having critical features employing phase shifting include techniques for providing a layout for shifters. The techniques include establishing placement of multiple pairs of shifters for a set of critical features. A critical feature employs phase shifting. The set of critical features constitutes a subset of all critical features in a layout. After establishing placement of the pairs of shifters, phase information for the shifters associated with the set of critical features is assigned. This and related techniques expedite resolving phase-shift conflicts in fabrication layouts for phase-shifted features.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: A two mask process for small dimension features on an integrated circuit improves manufacturability and design tolerance. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table.

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout.

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A method of assigning phases to shifters on a layout is provided. The method includes creating a link between any two shifters within a predetermined distance from each other. In one embodiment, the predetermined distance is larger than a minimum feature size on the layout, and smaller than a combined minimum pitch and regulator width. A weight can be assigned to each created link. Phases can be assigned to the shifters, wherein if a phase-shift conflict exists on the layout, then one or more links can be broken based on their weight.

Abstract: A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout.

Abstract: A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.

Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.