Patents by Inventor Yaocheng Liu

Yaocheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059316
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Patent number: 8642434
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Patent number: 8217423
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R Holt, Renee T Mo, Kern Rim
  • Publication number: 20120149159
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Publication number: 20120146092
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Patent number: 7932144
    Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Shreesh Narasimha, Katsunori Onishi, Kern Rim
  • Patent number: 7888197
    Abstract: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, William K. Henson, Yaocheng Liu
  • Patent number: 7838932
    Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Dureseti Chidambarrao, Judson R. Holt, Yaocheng Liu, Kern Rim
  • Patent number: 7741658
    Abstract: The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: June 22, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Zhijiong Luo, Huilong Zhu
  • Patent number: 7714358
    Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Shreesh Narasimha, Katsunori Onishi, Kern Rim
  • Publication number: 20100112766
    Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Applicant: International Business Machines Corporation
    Inventors: Yaocheng Liu, Shreesh Narasimha, Katsunori Onishi, Kern Rim
  • Patent number: 7709910
    Abstract: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: William K. Henson, Paul Chung-Muh Chang, Dureseti Chidambarrao, Ricardo A. Donaton, Yaocheng Liu, Shreesh Narasimha, Amanda L. Tessier
  • Patent number: 7696000
    Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Subramanian S. Iyer, Jinghong Li
  • Patent number: 7675118
    Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Yaocheng Liu, William K. Henson
  • Patent number: 7667263
    Abstract: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Zhijiong Luo, Yaocheng Liu
  • Patent number: 7655551
    Abstract: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Alexander Reznicek, Devendra K. Sadana
  • Patent number: 7632724
    Abstract: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: December 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, William K. Henson, Yaocheng Liu
  • Patent number: 7615435
    Abstract: A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Sameer Jain, Yaocheng Liu
  • Patent number: 7598147
    Abstract: A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Qiqing C. Ouyang, Kathryn T. Schonenberg, Chun-Yung Sung
  • Publication number: 20090181508
    Abstract: A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed in the trenches. During the forming of the Carbon-doped Silicon lattice structures Carbon atoms can be positioned in any substitutional sites within the lattice structures. The Carbon-doped Silicon lattice structures are then amorphized by implantation of an amorphizing species. An annealing process then recrystallizes the amorphized regions by solid-phase epitaxy regrowth to form the source and drain regions. During the annealing, a majority of Carbon atoms are substitutionally incorporated into a Silicon lattice of the source and drain regions to provide tensile stress to the channel region.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 16, 2009
    Applicant: International Business Machines Corporation
    Inventors: Judson R. Holt, Yaocheng Liu, Kern Rim