Abstract: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region.

Abstract: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Abstract: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.

Abstract: A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having a first stress located over the gate electrode and a second stressed layer having a second stress different than the first stress located over the first stressed layer. At least a portion of the first stressed layer is laterally contained by the spacer layer. At least a portion of the second stressed layer is not laterally contained by the spacer layer.

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract: A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.

Abstract: An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.

Abstract: Expitaxial substitutional solid solutions of silicon carbon can be obtained by an ultrafast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1?yCy, y<0.1 is desired for strain engineering or bandgap engineering.

Abstract: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

Abstract: The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract: In a fuel cell comprising a tubular casing, an electrolyte layer received in the tubular casing, and a pair of gas diffusion electrodes interposing the electrolyte layer and defining a fuel gas passage and an oxidizing gas passage, respectively, each gas diffusion electrode is formed by stacking a plurality of layers of material therefor, for instance in the axial direction of the casing. Because the gas diffusion layers are formed layer by layer, components can be formed in highly fine patterns so that a highly compact tubular fuel cell can be achieved. Similarly, the dimensions of the various elements of the fuel cell can be controlled in a highly accurate manner. Also, the geometric arrangement can be changed at will in intermediate parts of each gas passage.

Abstract: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location.

Abstract: In a fuel cell comprising a tubular casing, an electrolyte layer received in the tubular casing, and a pair of gas diffusion electrodes interposing the electrolyte layer and defining a fuel gas passage and an oxidizing gas passage, respectively, each gas diffusion electrode is formed by stacking a plurality of layers of material therefor, for instance in the axial direction of the casing. Because the gas diffusion layers are formed layer by layer, components can be formed in highly fine patterns so that a highly compact tubular fuel cell can be achieved. Similarly, the dimensions of the various elements of the fuel cell can be controlled in a highly accurate manner. Also, the geometric arrangement can be changed at will in intermediate parts of each gas passage.

Abstract: In a fuel cell assembly comprising a plurality of cell each including an electrolyte layer (2), a pair of diffusion electrode layers (3, 4) interposing the electrolyte layer between them, and a pair of flow distribution plates (5) for defining passages (11) for fuel and oxidant fluids that contact the diffusion electrode layers, the fuel cells are arranged on a common plane. Therefore, the vertical dimension of the fuel cell assembly can be minimized, and a fuel cell assembly of favorable electric properties can be achieved. Each flow distribution plate is typically formed with communication passages for communicating fluid passages defined on each side of the electrolyte layer at a prescribed pattern. The communication passages and through holes communicate the fluid passages in such a manner that adjacent fuels cells have opposite polarities.

Abstract: A fuel cell contains an electrolyte sheet sandwiched between two electrodes. One or both electrode/electrolyte interfaces includes mesoscopic three-dimensional features in a prescribed pattern. The features increase the surface area-to-volume ratio of the device and can be used as integral channels for directing the flow of reactant gases to the reaction surface area, eliminating the need for channels in sealing plates surrounding the electrodes. The electrolyte can be made by micromachining techniques that allow very precise feature definition. Both selective removal and mold-filling techniques can be used. The fuel cell provides significantly enhanced volumetric power density when compared with conventional fuel cells.