Patents by Inventor Yashodhan Vijay Moghe
Yashodhan Vijay Moghe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369421Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.Type: ApplicationFiled: July 12, 2023Publication date: November 16, 2023Applicant: Silanna Asia Pte LtdInventors: Stuart B. Molin, George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Patent number: 11742396Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.Type: GrantFiled: November 8, 2021Date of Patent: August 29, 2023Assignee: Silanna Asia Pte LtdInventors: Stuart B. Molin, George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Publication number: 20230238955Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.Type: ApplicationFiled: March 24, 2023Publication date: July 27, 2023Applicant: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Patent number: 11641203Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.Type: GrantFiled: October 8, 2021Date of Patent: May 2, 2023Assignee: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Publication number: 20220059663Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Applicant: Silanna Asia Pte LtdInventors: Stuart B. Molin, George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Publication number: 20220029621Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.Type: ApplicationFiled: October 8, 2021Publication date: January 27, 2022Applicant: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Patent number: 11171215Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.Type: GrantFiled: April 27, 2020Date of Patent: November 9, 2021Assignee: Silanna Asia Pte LtdInventors: Stuart B. Molin, George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Patent number: 11146265Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.Type: GrantFiled: July 12, 2019Date of Patent: October 12, 2021Assignee: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Publication number: 20200258988Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Applicant: Silanna Asia Pte LtdInventors: Stuart B. Molin, George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Patent number: 10636905Abstract: An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.Type: GrantFiled: December 28, 2018Date of Patent: April 28, 2020Assignee: Silanna Asia Pte LtdInventors: George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Publication number: 20190334520Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.Type: ApplicationFiled: July 12, 2019Publication date: October 31, 2019Applicant: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Patent number: 10355688Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.Type: GrantFiled: December 6, 2017Date of Patent: July 16, 2019Assignee: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Publication number: 20190173465Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Applicant: Silanna Asia Pte LtdInventors: Cameron Brown, Yashodhan Vijay Moghe
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Publication number: 20190148544Abstract: An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.Type: ApplicationFiled: December 28, 2018Publication date: May 16, 2019Inventors: George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Patent number: 10192983Abstract: An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.Type: GrantFiled: January 16, 2017Date of Patent: January 29, 2019Assignee: Silanna Asia Pte LtdInventors: George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Patent number: 9748207Abstract: An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.Type: GrantFiled: December 21, 2016Date of Patent: August 29, 2017Assignee: The Silanna Group Pty LtdInventors: Norbert Krause, Yashodhan Vijay Moghe
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Patent number: 9742391Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.Type: GrantFiled: April 17, 2013Date of Patent: August 22, 2017Assignee: The Silanna Group PTY LTDInventors: Yashodhan Vijay Moghe, Andrew Terry
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Publication number: 20170162658Abstract: An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.Type: ApplicationFiled: January 16, 2017Publication date: June 8, 2017Applicant: Silanna Asia Pte LtdInventors: George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
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Publication number: 20170103969Abstract: An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Applicant: THE SILANNA GROUP PTY LTDInventors: Norbert Krause, Yashodhan Vijay Moghe
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Publication number: 20170093282Abstract: A power converter with a high side transistor and a low side transistor produces a phase voltage as the high and low side transistors turn on and off under control of a high side driver and a low side driver, respectively. The low side transistor has a low threshold voltage of 0.4 volts or less. In some embodiments, a drive voltage less than 0 volts turns off the low side transistor. In some embodiments, a low impedance between the low side driver and the low side transistor enables the drive voltage to turn off the low side transistor during high output transients. In some embodiments, the high side transistor, the low side transistor, the high side driver, and the low side driver are integrated together on the same integrated circuit die.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventor: Yashodhan Vijay Moghe