Abstract: A power converter with a high side transistor and a low side transistor produces a phase voltage as the high and low side transistors turn on and off under control of a high side driver and a low side driver, respectively. The low side transistor has a low threshold voltage of 0.4 volts or less. In some embodiments, a drive voltage less than 0 volts turns off the low side transistor. In some embodiments, a low impedance between the low side driver and the low side transistor enables the drive voltage to turn off the low side transistor during high output transients. In some embodiments, the high side transistor, the low side transistor, the high side driver, and the low side driver are integrated together on the same integrated circuit die.

Abstract: A semiconductor device includes a semiconductor die, a power switch, a gate driver, and decoupling capacitor. The power switch includes a power FET having a plurality of power FET segments formed in the semiconductor die. The gate driver has a plurality of gate driver segments formed in the semiconductor die, at least a portion of the gate driver segments being distributed among the power FET segments. The decoupling capacitor has a plurality of decoupling capacitor segments formed in the semiconductor die, the decoupling capacitor segments being distributed among the gate driver segments.

Abstract: First and second communication interfaces receive and transmit first and second communications through isolation circuitry at different communication frequency levels. In some embodiments, the first and second communication interfaces are USB 3 compatible, and the isolation circuitry is between the first and second communication interfaces and is compatible with all USB 3 communication modes.

Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.

Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.

Abstract: A USB isolator integrated circuit, including: an isolation barrier disposed between an upstream portion and a downstream portion of the integrated circuit to provide galvanic isolation therebetween; a first USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the upstream portion of the integrated circuit and an upstream USB entity; a second USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the downstream portion of the integrated circuit and a downstream USB entity; a plurality of signal coupling components configured to allow communication between the upstream portion and the downstream portion of the integrated circuit to allow the upstream USB entity and the downstream USB entity to communicate therebetween using a USB 2.0 protocol while maintaining the galvanic isolation therebetween; and the upstream and downstream portions of the integrated circuit including respective modules configured to automatically detect a USB 2.

Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.