Abstract: A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.

Abstract: Disclosed is a clock signal generating integrated circuit device comprising a quartz crystal oscillator section and a multistage frequency divider section. The crystal oscillator section and each frequency divider stage includes respectively complementary insulated gate field effect transistors. According to the present invention, the high frequency-operated field effect transistors have a lower threshold voltage than the remaining field effect transistors, so that the occupied area of the oscillator section can be decreased and simultaneously the power dissipation can also be reduced.

Abstract: A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse .phi.1 and a reading-out clock pulse .phi.2 supplied in common thereto and receiving output signals from a Read Only Memory constructed in the form of a matrix. This Read Only Memory is constituted by a plurality of logical gate circuits each supplied with a plurality of prescribed signals of a pulse signal group having a plurality of input signals I1, I2, . . . In and control pulse signals T8, D4, A and B different in frequency from the clock pulses .phi.1 and .phi.2.

Abstract: A series logic circuit arrangement using a plurality of complementary IGFET's and comprising a plurality of series connected logic circuits, each of the logic circuits being designed to effect a predetermined logic function with respect to input binary coded signals by using at least one P channel IGFET and one N channel IFGET. In the negative logic system, the P channel IGFET's are arranged on a semiconductor substrate according to a logic equation of minterm-type expression, and the N channel IGFET's are arranged on the substrate according to a logic equation of maxterm-type expression, and, in the positive logic system, the N channel IGFET's are provided on the substrate according to the logic equation of minterm-type expression, and the P channel IGFET's are disposed on the substrate according to the logic equation of maxterm-type expression, thereby admitting of integrating the P and N channel IGFET's on the substrate within a smallest possible area.

Abstract: A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.