Abstract: A light emitting device includes a semiconductor light source device including a plurality of semiconductor light emitting elements, a wavelength conversion member that converts a wavelength of irradiation light from the semiconductor light source device, a concentrating lens that concentrates the irradiation light from the semiconductor light source device, and a cylindrical holder. The semiconductor light source device, the wavelength conversion member and the concentrating lens is supported by a support portion provided in an inner diameter portion of the cylindrical holder.

Abstract: A light emitting device includes a semiconductor light source device including a plurality of semiconductor light emitting elements, a wavelength conversion member that converts a wavelength of irradiation light from the semiconductor light source device, a concentrating lens that disposed between the semiconductor light source device and the wavelength conversion member and concentrates the irradiation light from the semiconductor light source device, and a cylindrical holder. The semiconductor light source device, the wavelength conversion member and the concentrating lens is supported by a support portion provided in an inner diameter portion of the cylindrical holder.

Abstract: A light emitting device includes at least a lens that emits light to the outside, a holder that supports the lens, and a wavelength conversion member and a semiconductor light source that are disposed inside the holder and a semiconductor light source on a side opposite to an emission surface of the lens, in which an inner wall of the holder between the lens and the wavelength conversion member includes a first step portion that covers an outer edge of the wavelength conversion member as seen from the lens side.

Abstract: A light emitting device includes a semiconductor light source device including a plurality of semiconductor light emitting elements, a wavelength conversion member that converts a wavelength of irradiation light from the semiconductor light source device, a concentrating lens that disposed between the semiconductor light source device and the wavelength conversion member and concentrates the irradiation light from the semiconductor light source device, and a cylindrical holder. The semiconductor light source device, the wavelength conversion member and the concentrating lens is supported by a support portion provided in an inner diameter portion of the cylindrical holder.

Abstract: A light emitting device includes a semiconductor light source device including a plurality of semiconductor light emitting elements, a wavelength conversion member that converts a wavelength of irradiation light from the semiconductor light source device, a concentrating lens that concentrates the irradiation light from the semiconductor light source device, and a cylindrical holder. The semiconductor light source device, the wavelength conversion member and the concentrating lens is supported by a support portion provided in an inner diameter portion of the cylindrical holder.

Abstract: A processor includes an acquisition unit configured to acquire a captured image from a camera and an image processing unit configured to recognize an object from a recognition image that is based on the captured image. The image processing unit determines a resolution level corresponding to a resolution for the recognition image based on a characteristic of the object.

Abstract: Provided is a backlight unit capable of reducing luminance unevenness. The backlight unit includes a plurality of dot light sources and a light guide plate in which a predetermined side surface serves as a light incident surface for introducing light from the plurality of dot light sources. The plurality of dot light sources are classified into a first light source group and a second light source group. A mount point of the first light source group and a mount point of the second light source group are displaced from each other in a thickness direction of the light guide plate. A total luminance of the first light source group is higher than a total luminance of the second light source group.

Abstract: Provided is a backlight unit capable of reducing luminance unevenness. The backlight unit includes a plurality of dot light sources and a light guide plate in which a predetermined side surface serves as a light incident surface for introducing light from the plurality of dot light sources. The plurality of dot light sources are classified into a first light source group and a second light source group. A mount point of the first light source group and a mount point of the second light source group are displaced from each other in a thickness direction of the light guide plate. A total luminance of the first light source group is higher than a total luminance of the second light source group.

Abstract: Provided is a backlight unit capable of increasing luminance and of reducing unevenness in luminance. The backlight unit includes: a light diffusing member provided to cover a light emitting element mounted on a surface of a substrate; and a first light reflective member having a hole portion opened larger in size than an outer shape of the light diffusing member, the first light reflective member being provided on the surface of the substrate while having the light diffusing member protrude from the hole portion. In addition, a second light reflective member is further provided on the surface of the substrate, and the second light reflective member covers at least a part of a region corresponding to a gap left between the light diffusing member and the hole portion of the first light reflective member.

Abstract: A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

Abstract: In a nonvolatile floating-gate semiconductor memory device, a word line voltage supply circuit is configured to be able to apply gate voltages to the same memory cells such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time. At least one of the word line voltage supply circuit and the bit line voltage supply circuit is set to be able to apply a voltage to the same memory cells for a longer application period at the first time than at and after the second time. With this configuration, the threshold voltage distribution of the memory cells is controlled to be narrow.

Abstract: In a nonvolatile floating-gate semiconductor memory device, a word line voltage supply circuit is configured to be able to apply gate voltages to the same memory cells such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time. At least one of the word line voltage supply circuit and the bit line voltage supply circuit is set to be able to apply a voltage to the same memory cells for a longer application period at the first time than at and after the second time. With this configuration, the threshold voltage distribution of the memory cells is controlled to be narrow.

Abstract: In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

Abstract: A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

Abstract: A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

Abstract: This nonvolatile semiconductor memory device includes a word line regulator circuit 22, which supplies a voltage to a word line, a program/erase control circuit 21, which outputs a write control signal to the word line regulator circuit 22, and a pulse voltage step width storage circuit 23, which stores information of a voltage increment &Dgr;Vg. The word line regulator circuit 22 supplies a voltage to a word line according to the write control signal from the program/erase control circuit 21 based on the information of a voltage increment &Dgr;Vg stored in the pulse voltage step width storage circuit 23. A voltage increment &Dgr;Vg by which a threshold voltage change of a memory cell becomes a predetermined voltage can be set for each chip by the pulse voltage step width storage circuit 23. Consequently, a highly reliable multi-valued write operation can be performed.

Abstract: In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

Abstract: In a memory cell array, a floating-gate field-effect transistor connected to a word line and a bit line is disposed in a matrix configuration. The floating-gate field-effect transistor is composed of a source and a drain formed inside a P-type well provided inside an N-type well on a P-type semiconductor substrate, a floating gate formed over between the source and the drain with a tunnel oxide interposed therebetween, and a control gate formed on the floating gate with an interlayer insulating film interposed therebetween. When an erasing pulse is applied, a voltage of 6V is applied to the P-type well with use of a first high-voltage pumping circuit, while a voltage of 9V is applied to the N-type well with use of a second high-voltage pumping circuit. This makes it possible to provide a highly reliable nonvolatile semiconductor memory device capable of preventing occurrence of latchup.

Abstract: In a nonvolatile semiconductor memory device, a voltage Vpp of 12 V applied to an external terminal is dropped by a resistance element of 3500 &OHgr; to a voltage Vrpin. Vrpin is inputted to a regulator circuit to output a stabilized voltage Vpll of 5 V, so that Vpll is applied to a common source line as an erase pulse voltage. Termination of a first erase pulse application is judged by a level detection circuit based on a result of comparison between a reference voltage Vref of 11 V and an input voltage Vrpin which begins with 5 V upon start of the erase operation. Thus, since a large voltage magnitude of the input voltage is secured, a variation in the threshold voltage of a memory cell after the termination of the first erase pulse application can be made small, thereby preventing degradation of the erase speed.

Abstract: In a nonvolatile semiconductor memory device, overerase-verify in an erase operation is conducted in units of bit lines in a batch. A cell current of a reference cell and voltage applied to a word line of a main cell are set so as to have a detection level at which there can be one or no memory cell having a threshold voltage of 0.5 V at time of one overerase-verify operation and a leak current of an unselected memory cell can be 1 &mgr; A or lower in a normal operation. Thus, the number of verify times in the overerase-verify is reduced to shorten period of time in the overerase-verify and thereby achieve high-speed erase. Furthermore, a cell current can be reduced to achieve lower power consumption.