Abstract: A control voltage applying circuit applies a voltage Vcc as a bias voltage Vbias to gates of cascade transistors Tr11 and Tr12 in high voltage operation. As a result, a drain voltage of transistors Tr13 and Tr14 becomes (Vcc−Vthn) under a severest condition, by which the OFF-leak characteristic is prevented from deteriorating. A voltage of 1.1 V is applied as the bias voltage Vbias in low voltage operation. By thus limiting the currents of the cascade transistors Tr11 and Tr12, the abilities of the transistors Tr13 and Tr14 for pull-in to Vss are reduced. As a result, little influence is exerted even when the transistor Tr14, which is turned off when the input signal “in” makes the transition to “H”, is momentarily turned on, and the output signal can promptly rise when a transistor Tr16 is turned on, allowing the delay time to be shortened in the low voltage operation.

Abstract: In a first step, “application of an erasing pulse” and “verification” are conducted so that all the memory cells in an erasing-target block are set to 3V or less. Consequently, generation of a memory cell with a negative threshold voltage is prevented, and accurate verification is conducted to ensure that all the memory cells in a block are brought in an erased state. In a second step, “application of an erasing pulse” is executed to set a threshold voltage of the most erase-slow memory cell to 1.5V or less. In this process, instead of conducting verification, the pulse is applied N times as large as the number of pulse application in the first step. In a third step, “application of a program pulse” and “verification” are conducted to execute a channel writing.

Abstract: A voltage level shifter circuit includes a first transistor having a source, a drain, and first and second gates; a second transistor having a source, a drain, and first and second gates; and a switching section for receiving an input signal and changing respective voltages to be applied to first and second nodes, wherein one of the source and the drain of each of the first and second transistors is connected to a third node, the first gate of each of the first and second transistors is connected to the third node, the other of the source and the drain of the first transistor and the second gate of the second transistor are connected to the first node, and the other of the source and the drain of the second transistor and the second gate of the first transistor are connected to the second node, the voltage level shifter circuit further including a resistance equivalent element having first and second ends, a high voltage being applied to the first end, and the second end being are connected to the third node.

Abstract: In an erase method for a nonvolatile semiconductor memory device in which a memory cell array is divided into blocks, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application are performed for memory cells connected to one word line in a certain block. When a memory cell excessively erased is found by the second verify operation, a soft program operation for the memory cell is performed after the second verify operation. The erase pulse application, the first verify operation, and the second verify operation are executed word line by word line in the block.

Abstract: A circuit for storing and latching defective address data representing an address of a defective portion occurring in a memory cell array of a nonvolatile semiconductor memory device having a redundant function. The circuit includes floating gate field effect transistors and latch circuits. Each floating gate field effect transistor assumes one of a high-threshold state and a low-threshold state, and has a threshold of 0 volts or less (e.g. 0 to −2.5 volts) when in the low-threshold state.

Abstract: A nonvolatile semiconductor storage device erasing method prevents an erroneous reading by suppressing a threshold voltage change of a memory cell due to substrate disturbance in an erase operation of the memory cell. In the erase operation of a selected block, a first positive voltage of +3 V is applied to word lines of an unselected block, and a reference voltage of 0 V is applied to odd-number sub-bit lines. Even-number sub-bit lines are brought into a floating state. Since the first positive voltage of 13 V is applied to a control gate through the word line, the memory cell in a low state of threshold voltage such as about 1.5 V is turned on. Thus, the turned-on memory cell forms a channel layer, which has the reference voltage of 0 V. Then, a potential difference between the control gate and the channel layer is reduced to a small value of 3V so that an electric field between a floating gate and the channel layer is decreased.

Abstract: In a defective address data storage circuit for a nonvolatile semiconductor memory, electrically erasable programmable memory cells are arranged in rows and columns. A plurality of word lines are connected to the memory cells in each row, while a plurality of bit lines are connected to the memory cells in each column. There are further provided a column decoder for selecting a bit line and a word line decoder circuit selecting a different word line in a different write operation of defective address data. Because a different word line is selected every writing of defective address data, a write voltage is only once applied to memory cells connected to an identical word line.

Abstract: A data programming method for a nonvolatile semiconductor storage device includes: a number of memory cells each having a control gate, drain and source with an electrically data-programmable, erasable floating gate, arranged matrix-wise in rows and columns forming a memory cell array; a multiple number of word lines, each being connected to the control gates of the memory cells in one row; and a multiple number of bit lines, each being connected to the drains of the memory cells in one column and also connected to the sources of the memory cells in the adjacent column so that each is shared by the two adjacent columns, forming a virtual ground type array, wherein three or more classes of data can be electrically written into each memory cell by differentiating the threshold level of the charge amount accumulated on the floating gate.

Abstract: A virtual ground type array has a number of electrically data-programmable, erasable memory cells, arranged matrix-wise in rows and columns. A multiple number of row lines are each connecting the control gates of memory cells located in one row and a multiple number of column lines are each commonly connecting the drain and source of memory cells constituting columns. The memory cells are programmed sequentially in the order of degree of the difference in charge amount in the floating gate from the erased state (data‘00’).

Abstract: A cloth cutting knife 16 is structured such that the length of the cutting edge thereof is set shorter than the length of the side sewing portions of a buttonhole to be formed, and a buttonhole having a length corresponding to the length of the right and left side sewing portions can be formed by moving up and down the cloth cutting knife 16 two or more times. The cloth cutting knife 16 is moved up and down at least once during formation of the stitches of the right and left side sewing portions. Also, the cloth cutting knife 16 is moved up and down once each time a given number of stitches of the right and left side sewing portions are formed. The given number of stitches is set in accordance with both of the length of the cutting edge of the cloth cutting knife 16 and the length of the buttonhole to be formed.

Abstract: Between a first negative voltage level shifter which is made up of transistors having a normal breakdown voltage and which shifts an input signal of a level Vcc or Vss to a level Vcc or Vnmin, and a second negative voltage level shifter which is made up of transistors having a normal breakdown voltage and which shifts an input signal of a level Vnmin or Vss to a level Vss or Vneg, is provided an inverter 8 for converting the level Vcc or Vnmin derived from the first negative voltage level shifter to the level Vnmin or Vss and then feeds the resulting voltage level to the second negative voltage level shifter. Vnmin, which is an intermediate level between Vss and Vneg, is set so that the maximum voltage difference of voltages applied to the transistors of the first negative voltage level shifter becomes equal to or smaller than the breakdown voltage.

Abstract: In a non-volatile semiconductor memory composed of floating gate field effect transistors arranged in rows and columns forming an array, a redundancy method is provided which includes the steps of: providing one or more column lines for redundancy, in which floating gate FETs in a number as many as the row lines of the array are connected; when a defect occurs in a column line, setting the thresholds of at least all the floating gate FETs connected to the defective column line, to the high state; and using as the substitute memory, the floating gate FETs for redundancy connected to redundancy column lines in a number as many as those of the floating gate FETs of which the thresholds are set in the high state.

Abstract: A latch circuit functions as a write latch circuit when writing a defective address into a nonvolatile semiconductor memory cell array. The latch circuit also functions as a defective address latch circuit when the power voltage rises. Therefore, the layout area of the defective address setting circuit can be reduced as compared with the defective address setting circuit of the conventional flash memory of the FN--FN type provided with a write latch circuit and a defective address latch circuit.

Abstract: For programming data "0", a reference voltage Vss (e.g., 0 V) is applied to a drain and a source of a memory cell to be programmed via a corresponding main bit line, a corresponding select transistor, and a corresponding local bit line, while a second voltage Vpp (e.g., 15 V) is applied to a control gate of the memory cell via a word line connected with the memory cell. As a result, electrons are injected from the drain, source and channel region to a floating gate of the memory cell via its tunnel oxide. For erasing the memory cell, a third voltage Vds (e.g., 0-6 V) is applied to a semiconductor substrate of the memory cell and a fourth voltage Vneg (e.g., -10 V) is applied to the control gate via the word line. At this time, the third voltage is also applied to the source and drain. Alternatively, the source and drain of the memory cell are placed in a floating state. Consequently, electrons are ejected from the floating gate to the channel region via the tunnel oxide.

Abstract: A non-volatile semiconductor memory device according to the present invention includes: a matrix of word lines and bit lines intersecting one another; and a memory cell of a stack gate type being disposed so as to correspond to each intersection of the matrix of the bit lines and the word lines, the memory cell including a control gate, a drain, and a source, the control gate being coupled to a corresponding one of the word line, the drain being coupled to a corresponding one of the bit lines, and the memory cell being capable of performing a write operation and an erase operation based on an FN tunnel phenomenon. Data is written to the memory cell by applying a reference voltage to the control gate, a first voltage to a well in which the memory cell is formed, and a second voltage to the drain; and data is erased from the memory cell by applying a third voltage to the control gate and the reference voltage to the well.

Abstract: A data writing circuit includes: a transfer gate (TG) selecting a bit line (BL0) of a virtually grounded cell array; a latch circuit (L) connected to the bit line (BL0) via the transfer gate (TG) for latching the data to be written, given to the bit line; a switching circuit (PM) which is connected between the bit line (BL0) and a program power source (VFROG) and is activated in accordance with the data to be written which has been latched by the latch circuit (L), to thereby supply the program power source (V.sub.PROG) to the bit line (BL0). This circuit, in accordance with the data to be written, sets the bit line (BL0) to which a memory cell (M) is connected, to a state of being applied by the program power source (V.sub.PROG) or a floating state.

Abstract: A buttonhole sewing machine includes a holding mechanism attached to a holder arm which reciprocates in a direction perpendicular to an amplitude direction of a needle. The holding mechanism includes a workpiece holder plate and constitutes a parallelogram linkage. The holding mechanism maintains a parallelogram shape even when the holder plate slants on a fold of the workpiece, and securely holds the workpiece. This buttonhole sewing machine also includes a cutting mechanism which cuts thread and braid in a short manner even when the holder plate slants. The cutting mechanism has a rotary cutter and a fixed cutter, and the fixed cutter is fixed on the holder plate while inclined from a proximal portion to a distal portion. A wire member is connected to the mobile cutter to facilitate the rotation of the rotary cutter even when the holder plate slants.

Abstract: The present invention has a structure wherein a word line erasing voltage is inhibited from being applied to a sector (each word line) in which it is decided that erasure has been completed. Consequently, a method for controlling erasure of a nonvolatile semiconductor memory is provided in which distribution of a threshold can be tight without increasing a layout area so that a threshold of a reference cell for erasure can be lowered, read can be performed without boosting the word line by using a power supply having a low voltage, and high-speed read and low power consumption can thus be realized.

Abstract: According to the present invention, a nonvolatile semiconductor storage device for applying to each word line either one of a selected voltage and a non-selected voltage, corresponding to a selection state and a non-selection state, respectively, is provided. The selection state or the non-selection state is selected in accordance with an address signal in each operational mode.