Patents by Inventor Yasue Tokutake
Yasue Tokutake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130048350Abstract: A base member includes: a core layer including: a plate-like body, made of aluminum oxide; and plural linear conductors, which penetrate through the plate-like body in a thickness direction of the plate-like body; a bonding layer, formed on at least one of a first surface and a second surface of the core layer; and a silicon layer or a glass layer, formed on the bonding layer.Type: ApplicationFiled: August 17, 2012Publication date: February 28, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda
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Patent number: 8362369Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.Type: GrantFiled: June 2, 2010Date of Patent: January 29, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Masao Nakazawa
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Publication number: 20120327626Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.Type: ApplicationFiled: June 21, 2012Publication date: December 27, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki
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Publication number: 20120313245Abstract: One embodiment provides a semiconductor device having: a core substrate having first and second surfaces and an accommodation hole penetrating therethrough; a semiconductor element accommodated in the accommodation hole so that a front surface thereof is on the first surface side; a first metal film formed on a back surface of the semiconductor element; a second metal film formed on the second surface of the core substrate; an insulating layer covering the first and second metal films; and a third metal film formed on the insulating layer, via parts thereof penetrating through the insulating layer to respectively reach the first and second metal films.Type: ApplicationFiled: June 11, 2012Publication date: December 13, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio HORIUCHI, Yasue TOKUTAKE, Yuichi MATSUDA
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Patent number: 8324513Abstract: A wiring substrate includes a core substrate including an inorganic dielectric insulating base material having first and second surfaces, and linear conductors penetrating the insulating base; a first wiring layer on the first surface electrically connected to a portion of linear conductors; a second wiring layer on the second surface electrically connected to the portion of the linear conductors; a first insulating layer on the first surface covering the first wiring layer and including a first through-hole; a third wiring layer on the first insulating layer electrically connected to the first wiring layer via the first through-hole; a second insulating layer on the second surface covering the second wiring layer and including a second through-hole; and a fourth wiring layer on the second insulating layer electrically connected to the second wiring layer via the second through-hole.Type: GrantFiled: January 20, 2011Date of Patent: December 4, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda
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Patent number: 8304664Abstract: An electronic component (chip) mounted structure includes a chip having a terminal, a wiring board having a terminal electrically connected to the terminal of the chip, and an interposing board disposed between the chip and the wiring board and having a structure including an insulating base material provided with a large number of filamentous conductors penetrating the insulating base material in a thickness direction thereof. The terminal of the chip is electrically connected to the terminal of the wiring board via a plurality of filamentous conductors provided in the interposing board.Type: GrantFiled: May 11, 2010Date of Patent: November 6, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tsuyoshi Kobayashi, Michio Horiuchi, Yukio Shimizu, Yasue Tokutake
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Patent number: 8304129Abstract: A solid electrolyte fuel cell comprising a cathode layer 12 formed on one side of a solid electrolyte layer 10 and an anode layer 18 formed on the other side of the solid electrolyte layer 10, wherein the cathode layer 16 comprises a first cathode layer 12 formed in contact with the solid electrolyte layer and a second cathode layer 14 formed covering the first cathode layer 12, the second cathode layer 14 is formed having a higher porosity than the first cathode layer 12 and the first cathode layer 12 is divided into a plurality of island-shaped portions 12a, 12a.Type: GrantFiled: March 27, 2007Date of Patent: November 6, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Fumimasa Katagiri, Shigeaki Suganuma, Yasue Tokutake, Jun Yoshiike, Michio Horiuchi
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Patent number: 8252477Abstract: A direct-flame fuel cell according to the invention has a cell in which a solid electrolyte 1 is sandwiched between an anode 2 and a cathode 3. The anode 2 contains one or more kinds of alkaline metal compounds or alkaline earth metal compounds which are effective in suppressing soot generation due to exposure to a flame. Where the anode 2 includes two or more layers 2a and 2b, the one or more kinds of alkaline metal compounds or alkaline earth metal compounds are contained in the outermost layer 2b.Type: GrantFiled: November 30, 2007Date of Patent: August 28, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Fumimasa Katagiri, Shigeaki Suganuma, Jun Yoshiike, Yasue Tokutake
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Patent number: 8242612Abstract: A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors.Type: GrantFiled: June 11, 2010Date of Patent: August 14, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
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Patent number: 8138609Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.Type: GrantFiled: July 8, 2010Date of Patent: March 20, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
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Patent number: 8057950Abstract: A solid oxide fuel cell includes: a solid electrolyte; and electrodes on both surfaces of the solid electrolyte, wherein at least one of joint surfaces where the solid electrolyte and the electrodes are in contact with each other is a roughened surface having at least two different types of surface roughness.Type: GrantFiled: May 19, 2006Date of Patent: November 15, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Yasue Tokutake, Shigeaki Suganuma, Misa Watanabe
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Patent number: 8053680Abstract: A wiring board includes a plate-shaped resin member; chip connection pads provided in the resin member, the chip connection pads having connection surfaces electrically connected to electrode pads provided on a semiconductor chip, the connection surfaces being situated in substantially the same plane as a first surface of the resin member, the first surface being a side where the semiconductor chip is mounted; pads provided in a portion of the resin member, the portion being situated outside an area where the chip connection pads are formed; lead wirings connected to the pads; and conductive wires sealed by the resin member, the conductive wires electrically connecting the chip connection pads and the pads to each other.Type: GrantFiled: February 27, 2009Date of Patent: November 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Fumimasa Katagiri, Yasue Tokutake, Naoyuki Koizumi, Shigeaki Suganuma, Michio Horiuchi
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Publication number: 20110175235Abstract: A wiring substrate includes a core substrate including an inorganic dielectric insulating base material having first and second surfaces, and linear conductors penetrating the insulating base; a first wiring layer on the first surface electrically connected to a portion of linear conductors; a second wiring layer on the second surface electrically connected to the portion of the linear conductors; a first insulating layer on the first surface covering the first wiring layer and including a first through-hole; a third wiring layer on the first insulating layer electrically connected to the first wiring layer via the first through-hole; a second insulating layer on the second surface covering the second wiring layer and including a second through-hole; and a fourth wiring layer on the second insulating layer electrically connected to the second wiring layer via the second through-hole.Type: ApplicationFiled: January 20, 2011Publication date: July 21, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda
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Publication number: 20110095419Abstract: There is provided a conductive film. The conductive film includes: an anodized layer having a plurality of through holes extending therethrough in its thickness direction; a plurality of linear conductors each formed in a corresponding one of the through holes and each having first and second protrusions protruding from the anodized layer, wherein at least one of the first and second protrusions is covered by a coating material; and an uncured thermosetting resin layer formed on the anodized layer to cover at least one of the first and second protrusions.Type: ApplicationFiled: October 21, 2010Publication date: April 28, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tsuyoshi Kobayashi, Tatsuaki Denda
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Publication number: 20110095433Abstract: There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers.Type: ApplicationFiled: October 21, 2010Publication date: April 28, 2011Applicant: Shinko Electric Industries Co., Ltd.Inventors: Michio HORIUCHI, Yasue TOKUTAKE, Yuichi MATSUDA, Tsuyoshi KOBAYASHI, Tatsuaki DENDA
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Publication number: 20110018144Abstract: A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors.Type: ApplicationFiled: June 11, 2010Publication date: January 27, 2011Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
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Publication number: 20110013340Abstract: A capacitor includes a dielectric substrate and a large number of filamentous conductors formed to penetrate through the dielectric substrate in a thickness direction thereof. An electrode is connected to only respective one ends of a plurality of filamentous conductors constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate, or in at least two positions on one of the surfaces. Further, an insulating layer is formed on each of both surfaces of the dielectric substrate so as to cover regions between the electrodes, and a conductor layer is formed on the corresponding insulating layer integrally with a desired number of electrodes.Type: ApplicationFiled: July 9, 2010Publication date: January 20, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTDInventors: Michio HORIUCHI, Yasue Tokutake, Yuichi Matsuda, Yukio Shimizu, Tomoo Yamasaki, Yuta Sakaguchi
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Publication number: 20110012266Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.Type: ApplicationFiled: July 8, 2010Publication date: January 20, 2011Inventors: Michio HORIUCHI, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki, Yuta Sakaguchi
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Publication number: 20100307808Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.Type: ApplicationFiled: June 2, 2010Publication date: December 9, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Michio HORIUCHI, Yasue TOKUTAKE, Yuichi MATSUDA, Masao NAKAZAWA
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Publication number: 20100294552Abstract: An electronic component (chip) mounted structure includes a chip having a terminal, a wiring board having a terminal electrically connected to the terminal of the chip, and an interposing board disposed between the chip and the wiring board and having a structure including an insulating base material provided with a large number of filamentous conductors penetrating the insulating base material in a thickness direction thereof. The terminal of the chip is electrically connected to the terminal of the wiring board via a plurality of filamentous conductors provided in the interposing board.Type: ApplicationFiled: May 11, 2010Publication date: November 25, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTDInventors: Tsuyoshi KOBAYASHI, Michio Horiuchi, Yukio Shimizu, Yasue Tokutake