Patents by Inventor Yasue Yamamoto
Yasue Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978516Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.Type: GrantFiled: April 11, 2022Date of Patent: May 7, 2024Assignee: SanDisk Technologies LLCInventors: Yanjie Wang, Ohwon Kwon, Kou Tei, Tai-Yuan Tseng, Yasue Yamamoto, Yonggang Wu, Guirong Liang
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Publication number: 20230326531Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.Type: ApplicationFiled: April 11, 2022Publication date: October 12, 2023Applicant: SanDisk Technologies LLCInventors: Yanjie Wang, Ohwon Kwon, Kou Tei, Tai-Yuan Tseng, Yasue Yamamoto, Yonggang Wu, Guirong Liang
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Patent number: 9373389Abstract: A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line.Type: GrantFiled: January 6, 2016Date of Patent: June 21, 2016Assignee: SOCIONEXT INC.Inventor: Yasue Yamamoto
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Publication number: 20160118108Abstract: A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line.Type: ApplicationFiled: January 6, 2016Publication date: April 28, 2016Inventor: Yasue Yamamoto
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Patent number: 8094498Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: GrantFiled: June 2, 2010Date of Patent: January 10, 2012Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki
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Patent number: 7884642Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: March 11, 2010Date of Patent: February 8, 2011Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20100238735Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: Panasonic CorporationInventors: Yasue YAMAMOTO, Masanori SHIRAHAMA, Yasuhiro AGATA, Toshiaki KAWASAKI
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Patent number: 7764108Abstract: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.Type: GrantFiled: October 26, 2007Date of Patent: July 27, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Shinichi Sumi, Yasue Yamamoto
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Patent number: 7755941Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: GrantFiled: January 9, 2008Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki
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Publication number: 20100164542Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Panasonic CorporationInventors: Yasuhiro AGATA, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7696779Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: September 26, 2006Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7623380Abstract: A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.Type: GrantFiled: September 25, 2006Date of Patent: November 24, 2009Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki
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Patent number: 7602231Abstract: A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.Type: GrantFiled: September 25, 2006Date of Patent: October 13, 2009Assignee: Panasonic CorporationInventors: Yasue Yamamoto, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki
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Publication number: 20090189226Abstract: An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor.Type: ApplicationFiled: October 8, 2008Publication date: July 30, 2009Inventors: Yasue YAMAMOTO, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki
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Patent number: 7535748Abstract: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.Type: GrantFiled: October 2, 2007Date of Patent: May 19, 2009Assignee: Panasonic CorporationInventors: Masanori Shirahama, Yasuhiro Agata, Yasue Yamamoto
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Patent number: 7518903Abstract: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.Type: GrantFiled: March 1, 2007Date of Patent: April 14, 2009Assignee: Panasonic CorporationInventors: Masanori Shirahama, Yasuhiro Agata, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20080205144Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.Type: ApplicationFiled: January 9, 2008Publication date: August 28, 2008Inventors: Yasue YAMAMOTO, Masanori SHIRAHAMA, Yasuhiro AGATA, Toshiaki KAWASAKI
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Patent number: 7397720Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.Type: GrantFiled: August 9, 2006Date of Patent: July 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichi Sumi, Hirohito Kikukawa, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Yasue Yamamoto
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Publication number: 20080150613Abstract: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.Type: ApplicationFiled: October 26, 2007Publication date: June 26, 2008Inventors: Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Shinichi Sumi, Yasue Yamamoto
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Publication number: 20080112210Abstract: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.Type: ApplicationFiled: October 2, 2007Publication date: May 15, 2008Inventors: Masanori SHIRAHAMA, Yasuhiro AGATA, Yasue YAMAMOTO