Patents by Inventor Yasuhide Shimizu
Yasuhide Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10992225Abstract: The present technology relates to a charge pump circuit that enables reduction of a circuit area. Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.Type: GrantFiled: January 16, 2019Date of Patent: April 27, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Daisuke Arima, Yasuhide Shimizu, Kazuki Goto
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Publication number: 20210050775Abstract: The present technology relates to a charge pump circuit that enables reduction of a circuit area. Provided is a charge pump circuit including: a first transistor; a second transistor to which a constant current is supplied; a third transistor connected to the first transistor and a voltage source; a fourth transistor group including N transistors arranged in a cascade on the first transistor side, the N transistors all including control terminals connected to the second transistor; a fifth transistor group including N transistors arranged in a cascade on the second transistor side, the N transistors all including control terminals connected to the second transistor; a first switch that connects the first transistor to the second transistor; a second switch that connects the first transistor to a ground node; a third switch that connects the third transistor to the fifth transistor group; and a fourth switch that connects the third transistor to the ground node.Type: ApplicationFiled: January 16, 2019Publication date: February 18, 2021Inventors: Daisuke Arima, Yasuhide Shimizu, Kazuki Goto
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Patent number: 8836561Abstract: A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.Type: GrantFiled: September 12, 2013Date of Patent: September 16, 2014Assignee: Sony CorporationInventors: Norifumi Kanagawa, Yasuhide Shimizu
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Publication number: 20140104087Abstract: A D/A conversion circuit includes: current generation circuits each including a constant current source configured to generate a current, a first MOSFET connected to the constant current source and configured to control a supply destination of the current, a first gate control section configured to exclusively supply a first voltage and a second voltage to a gate of the first MOSFET, and a first discharge switch connected to the first gate control section and the gate of the first MOSFET, controlled to be turned on at the same time as the first gate control section supplies the second voltage and controlled to be turned off before the first gate control section supplies the first voltage; a first current addition line; a discharge line; a first resistor connected to the first current addition line; and a voltage source configured to supply the second voltage to the first gate control sections.Type: ApplicationFiled: September 12, 2013Publication date: April 17, 2014Applicant: SONY CORPORATIONInventors: Norifumi Kanagawa, Yasuhide Shimizu
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Patent number: 8692701Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.Type: GrantFiled: August 30, 2012Date of Patent: April 8, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Shoji Kawahito, Sung Wook Jung, Osamu Kobayashi, Yasuhide Shimizu, Takahiro Miki, Takashi Morie, Hirotomo Ishii
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Patent number: 8525718Abstract: Disclosed herein is a differential amplifier including: an input terminal configured to receive an input signal; an output terminal configured to output an output signal obtained as a result of amplifying the input signal; an amplification part configured to amplify the input signal to generate the output signal; a load circuit which is connected between the amplification part and a power-supply terminal, and is provided with a first-conduction transistor, and a changeover switch configured to switch a connection between a gate electrode of the first-conduction transistor and a drain electrode of the first-conduction transistor to a connection between the gate electrode and the output terminal or vice versa; and a leak cancel switch configured to generate a leak cancel current for reducing an off leak current flowing through the changeover switch.Type: GrantFiled: March 2, 2012Date of Patent: September 3, 2013Assignee: Sony CorporationInventors: Kouhei Kudou, Yasuhide Shimizu, Norifumi Kanagawa, Shigemitsu Murayama
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Patent number: 8497794Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.Type: GrantFiled: March 30, 2012Date of Patent: July 30, 2013Assignee: Sony CorporationInventors: Shinichirou Etou, Yasuhide Shimizu, Kouhei Kudou, Yukitoshi Yamashita
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Patent number: 8487801Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.Type: GrantFiled: March 30, 2012Date of Patent: July 16, 2013Assignee: Sony CorporationInventors: Shinichirou Etou, Yasuhide Shimizu, Kouhei Kudou, Yukitoshi Yamashita
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Patent number: 8427354Abstract: Disclosed herein is an analog to digital converter including an analog to digital conversion stage of at least one stage adapted to produce digital data of a value corresponding to a relationship to two analog signals inputted thereto and output two analog residual signals. The analog to digital conversion stage includes a signal production section, a comparison section, a first outputting section, a second outputting section, and a changeover section. The comparison section outputs first digital data when a first comparison result that the voltage value of the first analog signal is lower than the voltage value of the second analog signal is obtained whereas the comparison section outputs second digital data when a second comparison result that the voltage value of the first analog signal is higher than the voltage value of the second analog signal is obtained.Type: GrantFiled: September 28, 2011Date of Patent: April 23, 2013Assignee: Sony CorporationInventors: Yasuhide Shimizu, Shinichiro Eto, Kohei Kudo
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Publication number: 20130057418Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.Type: ApplicationFiled: August 30, 2012Publication date: March 7, 2013Inventors: Shoji KAWAHITO, Sung Wook JUNG, Osamu KOBAYASHI, Yasuhide SHIMIZU, Takahiro MIKI, Takashi MORIE, Hirotomo ISHII
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Publication number: 20120268300Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.Type: ApplicationFiled: March 30, 2012Publication date: October 25, 2012Applicant: Sony CorporationInventors: Shinichirou Etou, Yasuhide Shimizu, Kouhei Kudou, Yukitoshi Yamashita
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Publication number: 20120268302Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.Type: ApplicationFiled: March 30, 2012Publication date: October 25, 2012Applicant: Sony CorporationInventors: Shinichirou Etou, Yasuhide Shimizu, Kouhei Kudou, Yukitoshi Yamashita
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Publication number: 20120242525Abstract: Disclosed herein is a differential amplifier including: an input terminal configured to receive an input signal; an output terminal configured to output an output signal obtained as a result of amplifying the input signal; an amplification part configured to amplify the input signal to generate the output signal; a load circuit which is connected between the amplification part and a power-supply terminal, and is provided with a first-conduction transistor, and a changeover switch configured to switch a connection between a gate electrode of the first-conduction transistor and a drain electrode of the first-conduction transistor to a connection between the gate electrode and the output terminal or vice versa; and a leak cancel switch configured to generate a leak cancel current for reducing an off leak current flowing through the changeover switch.Type: ApplicationFiled: March 2, 2012Publication date: September 27, 2012Applicant: Sony CorporationInventors: Kouhei Kudou, Yasuhide Shimizu, Norifumi Kanagawa, Shigemitsu Murayama
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Publication number: 20120092203Abstract: Disclosed herein is an analog to digital converter including an analog to digital conversion stage of at least one stage adapted to produce digital data of a value corresponding to a relationship to two analog signals inputted thereto and output two analog residual signals. The analog to digital conversion stage includes a signal production section, a comparison section, a first outputting section, a second outputting section, and a changeover section. The comparison section outputs first digital data when a first comparison result that the voltage value of the first analog signal is lower than the voltage value of the second analog signal is obtained whereas the comparison section outputs second digital data when a second comparison result that the voltage value of the first analog signal is higher than the voltage value of the second analog signal is obtained.Type: ApplicationFiled: September 28, 2011Publication date: April 19, 2012Applicant: Sony CorporationInventors: Yasuhide Shimizu, Shinichiro Eto, Kohei Kudo
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Patent number: 8120388Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.Type: GrantFiled: January 18, 2007Date of Patent: February 21, 2012Assignee: Sony CorporationInventors: Yasuhide Shimizu, Shigemitsu Murayama, Yukitoshi Yamashita, Junji Toyomura
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Patent number: 8018368Abstract: An analog to digital converter includes: a reference circuit adapted to generate reference voltages; differential amplifiers; normal phase circuits each of which samples a normal phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a first input terminal of one of the differential amplifiers when the input is differential and single-ended; and reversed phase circuits each of which samples a reversed phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a second input terminal of one of the differential amplifiers when the input is differential and which samples a ground level as a reference voltage of the reference circuit and supplies the reference voltage and comparison voltage to the second input terminal of the differential amplifier when the input is single-ended.Type: GrantFiled: March 29, 2010Date of Patent: September 13, 2011Assignee: Sony CorporationInventors: Shigemitsu Murayama, Yasuhide Shimizu, Hiroaki Yatsuda, Kohei Kudo
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Patent number: 7898449Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.Type: GrantFiled: September 18, 2009Date of Patent: March 1, 2011Assignee: Semiconductor Technology Academic Research CenterInventors: Shoji Kawahito, Kazutaka Honda, Yasuhide Shimizu, Kuniyuki Tani, Akira Kurauchi, Koji Sushihara, Koichiro Mashiko
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Patent number: 7834786Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.Type: GrantFiled: May 6, 2009Date of Patent: November 16, 2010Assignee: Semiconductor Technology Academic Research CenterInventors: Shoji Kawahito, Zheng Liu, Yasuhide Shimizu, Kuniyuki Tani, Akira Kurauchi, Koji Sushihara, Koichiro Mashiko
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Publication number: 20100271244Abstract: An analog to digital converter includes: a reference circuit adapted to generate reference voltages; differential amplifiers; normal phase circuits each of which samples a normal phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a first input terminal of one of the differential amplifiers when the input is differential and single-ended; and reversed phase circuits each of which samples a reversed phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a second input terminal of one of the differential amplifiers when the input is differential and which samples a ground level as a reference voltage of the reference circuit and supplies the reference voltage and comparison voltage to the second input terminal of the differential amplifier when the input is single-ended.Type: ApplicationFiled: March 29, 2010Publication date: October 28, 2010Applicant: Sony CorporationInventors: Shigemitsu Murayama, Yasuhide Shimizu, Hiroaki Yatsuda, Kohei Kudo
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Patent number: 7696916Abstract: A parallel type analog-to-digital conversion circuit, including a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.Type: GrantFiled: August 27, 2008Date of Patent: April 13, 2010Assignee: Sony CorporationInventors: Yasuhide Shimizu, Shigemitsu Murayama, Kohei Kudo, Hiroaki Yatsuda