Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract: A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Abstract: A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a different pair formed of a plurality of sets of cascade-connected transistors, and has a first switch for short-circuiting respective cascade connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair.

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract: In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m?1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N?m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract: In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

Abstract: An oscillator circuit having a closed loop connection, including: an oscillator for generating an output signal oscillating at a frequency corresponding to a control signal; a frequency/voltage converter for generating a detection signal having a voltage corresponding to a frequency of the output signal; a difference detector for generating a difference signal indicating a difference between the detection signal and a reference signal; and an integrator for generating the control signal by integrating the difference signal.

Abstract: A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Abstract: A parallel type analog-to-digital conversion circuit, including a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.

Abstract: A semiconductor device includes a semiconductor substrate and a ladder resistor formed on the semiconductor substrate. The ladder resistor includes a plurality of elongated resistor portions arranged in parallel with each other, a plurality of connection portions that connect the resistor portions at predetermined intervals in a longitudinal direction of the resistor portions, and a plurality of voltage extraction portions provided in order to extract voltages at the individual connection portions.

Abstract: A flash A/D converter includes a reference voltage generator for generating a plurality of reference voltages, a first group of amplifiers having a plurality of amplifiers each of which amplifies a difference voltage between each reference voltage generated by the reference voltage generator and a voltage of an input signal, and a second group of amplifiers having a plurality of amplifiers. Each amplifier of the first group of amplifiers is a differential amplifier having a differential pair formed of a plurality of sets of cascode-connected transistors, and has a first switch for short-circuiting respective cascode connection portions of the plurality of transistors configuring the differential pair. Each amplifier of the second group of amplifiers is a differential amplifier having a differential pair formed of at least two transistors and has a second switch for short-circuiting a portion between input units of the differential pair.

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m?1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N?m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A semiconductor device includes a semiconductor substrate and a ladder resistor formed on the semiconductor substrate. The ladder resistor includes a plurality of elongated resistor portions arranged in parallel with each other, a plurality of connection portions that connect the resistor portions at predetermined intervals in a longitudinal direction of the resistor portions, and a plurality of voltage extraction portions provided in order to extract voltages at the individual connection portions.

Abstract: A differential amplifier device is disclosed wherein the device comprises a differential amplifier circuit, a load circuit connected to the differential amplifier circuit; and a change-over switch connected to the load circuit for changing a gain of the differential amplifier circuit by switching between a full load where a whole of the load circuit is set to be the load of the differential amplifier circuit and a partial load where a part of the load circuit is set to be the load of the differential amplifier circuit, wherein the load circuit is configured to amplify an input signal and an output signal of the differential amplifier circuit in the full load.

Abstract: An oscillator circuit having a closed loop connection, including: an oscillator for generating an output signal oscillating at a frequency corresponding to a control signal; a frequency/voltage converter for generating a detection signal having a voltage corresponding to a frequency of the output signal; a difference detector for generating a difference signal indicating a difference between the detection signal and a reference signal; and an integrator for generating the control signal by integrating the difference signal.

Abstract: A differential amplifier has an in-phase input terminal to which an input signal is applied through a first switching unit, an anti-phase input terminal to which a reference signal is applied through a second switching unit, and a third switching unit between the in-phase and anti-phase input terminals. The potential difference between the in-phase and anti-phase input terminals is differentially amplified by setting the first and second switching units to be on and the third switching unit to be off. Also, the in-phase and anti-phase input terminals are short-circuited to have a high impedance by setting the first and second switching units to be off and the third switching unit to be on.

Abstract: A differential amplifier device is disclosed wherein the device comprises a differential amplifier circuit, a load circuit connected to the differential amplifier circuit; and a change-over switch connected to the load circuit for changing a gain of the differential amplifier circuit by switching between a full load where a whole of the load circuit is set to be the load of the differential amplifier circuit and a partial load where a part of the load circuit is set to be the load of the differential amplifier circuit, wherein the load circuit is configured to amplify an input signal and an output signal of the differential amplifier circuit in the full load.