Patents by Inventor Yasuhiko Kawashima
Yasuhiko Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210257376Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.Type: ApplicationFiled: April 16, 2021Publication date: August 19, 2021Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
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Patent number: 11011530Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.Type: GrantFiled: June 7, 2019Date of Patent: May 18, 2021Assignee: FLOADIA CORPORATIONInventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
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Patent number: 10680001Abstract: In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.Type: GrantFiled: June 17, 2015Date of Patent: June 9, 2020Assignee: FLOADIA CORPORATIONInventors: Yasuhiro Taniguchi, Yasuhiko Kawashima, Hideo Kasai, Yutaka Shinagawa, Ryotaro Sakurai, Kosuke Okuyama
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Patent number: 10615168Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.Type: GrantFiled: August 14, 2019Date of Patent: April 7, 2020Assignee: FLOADIA CORPORATIONInventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi
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Publication number: 20190371799Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
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Patent number: 10431589Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.Type: GrantFiled: July 21, 2016Date of Patent: October 1, 2019Assignee: FLOADIA CORPORATIONInventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi
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Publication number: 20190296030Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.Type: ApplicationFiled: June 7, 2019Publication date: September 26, 2019Inventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
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Patent number: 10381446Abstract: A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers are respectively disposed in a first sidewall spacer and a second sidewall spacer, to separate a memory gate electrode and a first select gate electrode from each other and the memory gate electrode and a second select gate electrode from each other. Hence, a breakdown voltage is improved around the memory gate electrode as compared with a conventional case in which the first sidewall spacer and the second sidewall spacer are simply made of insulating oxide films. The nitride sidewall layers are disposed farther from a memory well than a charge storage layer. Hence, charge is unlikely to be injected into the nitride sidewall layers at charge injection from the memory well into the charge storage layer, thereby preventing an operation failure due to charge storage in a region other than the charge storage layer.Type: GrantFiled: May 27, 2016Date of Patent: August 13, 2019Assignee: FLOADIA CORPORATIONInventors: Yasuhiro Taniguchi, Fukuo Owada, Yasuhiko Kawashima, Shinji Yoshida, Kosuke Okuyama
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Patent number: 10373967Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.Type: GrantFiled: December 7, 2016Date of Patent: August 6, 2019Assignee: FLOADIA CORPORATIONInventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
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Patent number: 10276727Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.Type: GrantFiled: April 26, 2016Date of Patent: April 30, 2019Assignee: FLOADIA CORPORATIONInventors: Fukuo Owada, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
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Patent number: 10263002Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.Type: GrantFiled: October 9, 2015Date of Patent: April 16, 2019Assignee: FLOADIA CORPORATIONInventors: Yasuhiro Taniguchi, Hideo Kasai, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Kosuke Okuyama
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Publication number: 20180308990Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.Type: ApplicationFiled: April 26, 2016Publication date: October 25, 2018Inventors: Fukuo OWADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
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Patent number: 10102911Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.Type: GrantFiled: December 11, 2015Date of Patent: October 16, 2018Assignee: FLOADIA CORPORATIONInventors: Hideo Kasai, Yasuhiro Taniguchi, Yutaka Shinagawa, Ryotaro Sakurai, Yasuhiko Kawashima, Kosuke Okuyama
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Publication number: 20180286875Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.Type: ApplicationFiled: December 7, 2016Publication date: October 4, 2018Applicant: Floadia CorporationInventors: Daisuke OKADA, Kazumasa YANAGISAWA, Fukuo OWADA, Shoji YOSHIDA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
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Patent number: 10074660Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.Type: GrantFiled: February 19, 2016Date of Patent: September 11, 2018Assignee: FLOADIA CORPORATIONInventors: Hideo Kasai, Yasuhiro Taniguchi, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Tatsuro Toya, Takanori Yamaguchi, Fukuo Owada, Shinji Yoshida, Teruo Hatada, Satoshi Noda, Takafumi Kato, Tetsuya Muraya, Kosuke Okuyama
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Patent number: 10074658Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.Type: GrantFiled: March 18, 2016Date of Patent: September 11, 2018Assignee: FLOADIA CORPORATIONInventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
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Patent number: 10038101Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.Type: GrantFiled: October 6, 2015Date of Patent: July 31, 2018Assignee: FLOADIA CORPORATIONInventors: Yutaka Shinagawa, Yasuhiro Taniguchi, Hideo Kasai, Ryotaro Sakurai, Yasuhiko Kawashima, Tatsuro Toya, Kosuke Okuyama
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Publication number: 20180211965Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.Type: ApplicationFiled: July 21, 2016Publication date: July 26, 2018Inventors: Shoji YOSHIDA, Fukuo OWADA, Daisuke OKADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kazumasa YANAGISAWA, Yasuhiro TANIGUCHI
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Publication number: 20180197958Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.Type: ApplicationFiled: May 27, 2016Publication date: July 12, 2018Inventors: Yasuhiro TANIGUCHI, Fukuo OWADA, Yasuhiko KAWASHIMA, Shinji YOSHIDA, Kosuke OKUYAMA
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Publication number: 20180083014Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.Type: ApplicationFiled: March 18, 2016Publication date: March 22, 2018Inventors: Yutaka SHINAGAWA, Yasuhiro TANIGUCHI, Hideo KASAI, Ryotaro SAKURAI, Yasuhiko KAWASHIMA, Tatsuro TOYA, Kosuke OKUYAMA