Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.

Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.

Abstract: In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.

Abstract: In an anti-fuse memory includes a rectifier element of a semiconductor junction structure in which a voltage applied from a memory gate electrode to a word line is applied as a reverse bias in accordance with voltage values of the memory gate electrode and the word line, and does not use a conventional control circuit. Hence, the rectifier element blocks application of a voltage from the memory gate electrode to the word line. Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.

Abstract: A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.

Abstract: In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.

Abstract: In a memory unit, voltages required for operations of a capacity transistor in a first well and a writing transistor in a second well are separately applied to a first deep well and a second deep well, without the voltages on the first deep well and the second deep well being restricted by each other. Thus, in the memory unit, each of a voltage difference between the first deep well and the first well and a voltage difference between the second deep well and the second well is made smaller than a voltage difference (18 [V]), at which a tunneling effect occurs, and accordingly a junction voltage between the first deep well and the first well and a junction voltage between the second deep well and the second well are low.

Abstract: An ink for ink-jet recording containing: a colorant; and a solvent mixture containing water and solvent A which is not water, wherein solvent A has a surface tension of 25 to 40 mN/m at 25° C.; a viscosity of 1 to 50 mPs·s at 25° C.; and a vapor pressure of not more than 133 Pa at 25° C., a content of solvent A is from not less than 50 to less than 90 weight % based on the total weight of the ink; and a content of water is from not less than 10 to less than 45 weight % based on the total weight of the ink.

Abstract: An ink for ink-jet recording containing: a colorant; and a set of solvent A and solvent B, provided that solvent B has a larger vapor pressure than solvent A, wherein the set of solvent A and solvent B has a maximum in viscosity by changing a mixing ratio of solvent A to solvent B; and a content of solvent A in weight (A(wt)) and a content of solvent B in weight (B(wt)) in the ink satisfy the following relationship: 50?[A(wt)/(A(wt)+B(wt))]×100?95.

Abstract: An ink jet recording apparatus for jetting ink onto a recording medium having: an ink cartridge; an ink jet recording head; and an ink supply tube which connects the ink cartridge and the ink jet recording head, wherein a driving frequency of the ink jet recording head is 15 kHz or above, and an average surface roughness of an inner surface of the ink supply tube is 200 to 2,000 nm.

Abstract: An ink for ink-jet recording containing: a colorant; and a solvent mixture containing water and solvent A which is not water, wherein solvent A has a surface tension of 25 to 40 mN/m at 25° C.; a viscosity of 1 to 50 mPs·s at 25° C.; and a vapor pressure of not more than 133 Pa at 25° C., a content of solvent A is from not less than 50 to less than 90 weight % based on the total weight of the ink; and a content of water is from not less than 10 to less than 45 weight % % based on the total weight of the ink.

Abstract: An ink for ink-jet recording containing: a colorant; and a set of solvent A and solvent B, provided that solvent B has a larger vapor pressure than solvent A, wherein the set of solvent A and solvent B has a maximum in viscosity by changing a mixing ratio of solvent A to solvent B; and a content of solvent A in weight (A(wt)) and a content of solvent B in weight (B(wt)) in the ink satisfy the following relationship: 50?[A(wt)/(A(wt)+B(wt))]×100?95.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.

Abstract: An ink jet recording apparatus for jetting ink onto a recording medium having: an ink cartridge; an ink jet recording head; and an ink supply tube which connects the ink cartridge and the ink jet recording head, wherein a driving frequency of the ink jet recording head is 15 kHz or above, and an average surface roughness of an inner surface of the ink supply tube is 200 to 2,000 nm.

Abstract: An ink-jet recording method of forming an image with an ink-jet head, wherein the ink-jet head includes an ink chamber, an electric actuator provided in the ink chamber and an insulating layer covering the electric actuator, including steps of: feeding an ink containing a coloring material and a water-soluble solvent into ink chamber, and applying a driving voltage with a driving frequency of 10 kHz to 55 kHz onto the electric actuator so that the ink is jetted from the ink chamber so as to form the image; wherein the thickness of the insulating layer is 0.1 &mgr;m to 10 &mgr;m, and the concentration of oxygen dissolved in the ink is 4 ppm or less.

Abstract: An ink-jet recording a water-based ink from an ink chamber through a nozzle hole, wherein the ink chamber contacting with the water-based ink is constructed by jointing plural construction members with an epoxy adhesive, and the water-based in contains a coloring material, a first organic solvent, and a second organic solvent each having properties of a specific organicity and inorganicity. This method enables to enhance the stability of ejection of ink droplets without shortening the life of the head.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.