Patents by Inventor Yasuhiko Kuriyama

Yasuhiko Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10250193
    Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: April 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 10153803
    Abstract: A receiving circuit includes a plurality input nodes to receive an input signals and an output node to output a signal corresponding to the input signal. An amplifier in the circuit has an input terminal and an output terminal. A first switch selectively connects one of the input nodes to the input terminal of the amplifier. A second switch selectively connects the one of the input nodes to the output node. A controller supplies control signals to the first switch and the second switch. An impedance matching section is connected between the input nodes and the amplifier.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: December 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sugawara, Toshiki Seshita, Yasuhiko Kuriyama
  • Publication number: 20180342988
    Abstract: A semiconductor device formed on a silicon on insulator substrate includes an input node to receive a first signal, such as a high frequency signal, and an output node to output a second signal corresponding to the first signal. A first transistor has a gate that receives the first signal from the input node and thereby outputs an amplified first signal. A second transistor is connected between a drain of the first transistor and the output node. An inductor is connected between a source of the first transistor and a ground potential. A capacitor connected is between the gate of the first transistor and the input node. An electrostatic discharge (ESD) protective element is connected between a first node and a second node. The first node is between the inductor and the first transistor, and the second node is between the input node and the capacitor.
    Type: Application
    Filed: August 28, 2017
    Publication date: November 29, 2018
    Inventors: Toshiki SESHITA, Yasuhiko KURIYAMA
  • Patent number: 10122356
    Abstract: A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 6, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yugo Kunishi, Yasuhiko Kuriyama, Yoshio Itagaki
  • Publication number: 20180294774
    Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Toshiki SESHITA, Yasuhiko KURIYAMA
  • Patent number: 10033332
    Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Publication number: 20180167039
    Abstract: An amplifier amplifies an input signal. A splitter branches an output signal of the amplifier into a first signal path and a second signal path and performs impedance conversion of the first and second signal paths. A first output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the first signal path by the splitter. A second output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the second signal path by the splitter. An output controller switches whether the output signal of the amplifier is output from the first output terminal, is output from the second output terminal, or is branched by the splitter to be output from both the first and second output terminals.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 14, 2018
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 9954493
    Abstract: A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Publication number: 20180083609
    Abstract: A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.
    Type: Application
    Filed: March 6, 2017
    Publication date: March 22, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yugo KUNISHI, Yasuhiko KURIYAMA, Yoshio ITAGAKI
  • Publication number: 20180083665
    Abstract: A receiving circuit includes a plurality input nodes to receive an input signals and an output node to output a signal corresponding to the input signal. An amplifier in the circuit has an input terminal and an output terminal. A first switch selectively connects one of the input nodes to the input terminal of the amplifier. A second switch selectively connects the one of the input nodes to the output node. A controller supplies control signals to the first switch and the second switch. An impedance matching section is connected between the input nodes and the amplifier.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 22, 2018
    Inventors: Mitsuru SUGAWARA, Toshiki SESHITA, Yasuhiko KURIYAMA
  • Publication number: 20180069508
    Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
    Type: Application
    Filed: February 27, 2017
    Publication date: March 8, 2018
    Inventors: Toshiki SESHITA, Yasuhiko KURIYAMA
  • Publication number: 20180062581
    Abstract: A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.
    Type: Application
    Filed: March 16, 2017
    Publication date: March 1, 2018
    Inventors: Toshiki SESHITA, Yasuhiko KURIYAMA
  • Patent number: 7595696
    Abstract: A power amplifier including an active device having at least one heterjunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor connected in series between one electrode of the diode and the base of the bipolar transistor; and a bias circuit connected between the diode and the resistor, wherein the bipolar transistor includes a plurality of transistors, and each transistor is connected to the bias circuit via a resistor connected to a base of the transistor. The bias circuit may include an emitter follower circuit having a bipolar transistor.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: September 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Sugiura, Yasuhiko Kuriyama
  • Patent number: 7247921
    Abstract: A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Sugiura, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe, Makoto Shibamiya
  • Publication number: 20070159246
    Abstract: A power amplifier includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; a resistor connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the diode and the resistor. A power amplifier may alternatively includes: an active device having at least one heterojunction bipolar transistor based on a compound semiconductor; a diode connected between the base and the emitter of the bipolar transistor in reverse direction with respect to the base-emitter diode; two resistors connected in series between the diode and the base of the bipolar transistor; and a bias circuit connected between the two resistors.
    Type: Application
    Filed: December 22, 2006
    Publication date: July 12, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Sugiura, Yasuhiko Kuriyama
  • Patent number: 7088183
    Abstract: A bias circuit supplying a bias current to a first transistor includes a second transistor having a collector connected to a first power supply and having an emitter connected to a base of the first transistor, a third transistor having a collector connected to the emitter of the second transistor and having an emitter connected to a second power supply, a voltage supply circuit supplying a base voltage to a base of the second transistor, a first resistor connecting the collector of the third transistor and a base thereof, and a capacitor connected between the base of the second transistor and the second power supply.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Kuriyama
  • Patent number: 7084708
    Abstract: A high-frequency amplification device includes a high-frequency amplifier including input and output sections, a first capacitor including first and second electrodes, and a first insulation film interposed therebetween. The first electrode is connected to the output section via a first inductor, and the second electrode is grounded. The amplification device further comprises a second capacitor including third and fourth electrodes and a second insulation film interposed therebetween. The third electrode is formed of a material substantially identical to that of the first electrode, and the fourth electrode is formed of a material substantially identical to that of the second electrode. The second insulation film is formed of a material substantially identical to that of the first insulation film and has a thickness substantially identical to that of the first insulation film.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: August 1, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Sugiura, Makoto Shibamiya, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe
  • Patent number: 7038546
    Abstract: A high-power amplification circuit includes a first transistor which amplifies an input signal, a bias circuit which includes a second transistor which is an emitter follower, and supplies a bias current to a base of the first transistor, a constant-voltage power supply connected to the base of the second transistor through a first resistor, a control voltage terminal input one of a first control and a second control voltage, a third transistor including a base connected to the control voltage terminal through a second resistor, a third resistor connected between the base of the second transistor and the collector of the third transistor, and a fourth transistor connected between the base of the second transistor and the third resistor, the fourth transistor being diode-connected.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Kuriyama
  • Patent number: 7009453
    Abstract: A bias current supply circuit according to an embodiment of the invention includes a first transistor and a second transistor which form two emitter followers cooperating to supply a base bias current of a bipolar transistor for signal amplification, a normal temperature characteristic circuit which has normal temperature characteristics increasing an amount of current supply with increasing temperature and supplies a base current to the first bipolar transistor, and a reverse temperature characteristic circuit which has reverse temperature characteristics decreasing the amount of current supply with increasing temperature and supplies a base current to the second bipolar transistor.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Kuriyama
  • Publication number: 20050275076
    Abstract: A semiconductor apparatus comprising: a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 15, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Sugiura, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe, Makoto Shibamiya