Abstract: There is provided a multi-functional peripheral which is easy for user to use. In the multi-functional peripheral, after a logical device control program retaining a function of a logical device to which the job is transmitted from an information processing apparatus and managing the job transmitted to the logical device is allowed to analyze the inputted job, a physical device control program retaining a function of a device engine of the peripheral and managing the job in the device engine is allowed to analyze the job.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: A method for designing an electronic logic circuit device for reducing delay time degradation due to crosstalk between a wire in question and a wire adjacent thereto and for preventing the increase of designing work in case signal arrival time of each of the wire in question and the adjacent wire is dynamically changed according to the input pattern.

Abstract: An electrophoresis apparatus in which an electrophoretic channel formed in a planar plate made of a transparent member and having satisfactory flat and smooth surfaces is irradiated with an excitation beam through the bottom surface or the top surfaces of the channel in a direction orthogonal thereto, and fluorescence from a sample is detected through a side surface of the channel, or the channel is irradiated with the excitation beam through a side surface of the channel while fluorescence from the sample is detected through the bottom surface or the top surface of the channel. With this arrangement, background light and stray light can be reduced so as to enhance the accuracy of detection of the electrophoresis apparatus.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, so their diffusion layers are shared. The PMOS and NMOS are staggered so that their gates are almost in line. With this arrangement, wires connecting drains of the PMOS and NMOS and wires connecting sources of the PMOS and NMOS do not intersect each other, so they can be wired with only the first wiring layer. Further, gate input signals can be wired with only polysilicon wires without crossing each other. The pass-transistor logic circuit is made to pass through the signal buffers before or after it is connected to the selector. This can make a compact, fast circuit.

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: A micro pump is made compact and can prevent members constituting the micro pump from being chemically reacted with a working fluid, and a method of producing the same. After each of substrates constituting the micro pump is formed by a member containing a silicone as a main composition and a plurality of metal membranes are formed on a whole of a bonding surface of each of the substrates so as to form bonding surfaces, the bonding surfaces are cleaned, and the bonding surfaces are opposed to each other under a vacuum condition, overlapped, heated and pressed so as to be bonded. The valve portion has a beam and a protrusion for sealing as provided in the valve side, whereby a pressure applied to the protrusion becomes smaller than the bonding pressure.

Abstract: A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: A chemical analyzing apparatus comprises a reaction cell holder which holds a plurality of reaction cells that are supplied with samples and reagents at a predetermined position, a measurer for measuring characteristics of the sample, a plurality of reagent containers, a liquid deliverer provided below each of the plurality of reagent containers, one or more sound wave generators provided outside the reaction cells, and storage containers for storing cleansing liquid with different contamination states. The cleansing liquid with different contamination states is reused according to the contamination levels of the reaction cells.

Abstract: Heretofore, there has been demanded an automatic analysis apparatus which can prevent cross-contamination between reagents, which can prevent dust and gas from entering a reagent supply device, which can always know a remaining quantity of the reagent while can reduce the quantity of waste. According to the present invention, there is provided an automatic analysis apparatus in which a reagent supply device for supplying a reagent from a reagent container into a reaction container is removably attached to the reagent container, a protective door is provided in the reagent supply port in order to aim at preventing dust from entering the reagent supply device, and further the reagent container and the reagent supply device are provided with recording mediums for recording therein conditions thereof, a time of replacement thereof or the like, and which can inform whether the setting is proper or not.