Abstract: There is provided with A flip-flop circuit for setting one of first and second storage nodes at one of first and second potential levels and the other storage node at the other potential level in accordance with stored data, and a switch circuit electrically coupling an internal node electrically coupled to a bit line to a first potential in accordance with the potential level of the one storage node.

Abstract: This three-valued inverter includes first and second P-channel MOS transistors connected in series between a line of a first power supply potential and an output node, and each having a gate receiving a first signal; third and fourth P-channel MOS transistors connected in series between a line of a second power supply potential and the output node, and each having a gate receiving a second signal; and an N-channel MOS transistor connected between the output node and a line of a ground potential, and having a gate receiving a third signal. Back gates of the first and third P-channel MOS transistors are applied with the first power supply potential and the second power supply potential, respectively, and back gates of the second and fourth P-channel MOS transistors are both connected to the output node. Therefore, even in a power-up period or the like, no latch-up occurs.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: A memory cell is formed of a sense access transistor for data sensing, a restore access transistor for data restoration and a memory capacitor for data storage. Sense access transistor couples the memory capacitor to a sense bit line according to a signal on a sense word line. The restore access transistor couples the memory capacitor to a restore bit line provided separate from the sense bit line according to a signal on a restore word line. Electric charges in the memory capacitor are transferred to a sense amplifier through the sense bit line and sense data in a sense amplifier is transferred to original memory capacitor through a restore amplifier and the restore access transistor. Output signal lines of the sense amplifier are electrically isolated from the sense and restore bit lines. Thereby, it is possible to reduce the access time of a semiconductor memory device.

Abstract: There is provided with A flip-flop circuit for setting one of first and second storage nodes at one of first and second potential levels and the other storage node at the other potential level in accordance with stored data, and a switch circuit electrically coupling an internal node electrically coupled to a bit line to a first potential in accordance with the potential level of the one storage node.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.

Abstract: There is provided a semiconductor memory device including eight memory blocks 20a to 20h, first data bus 22a, and second data bus 22b. The eight memory blocks are arranged at respective eight of the total nine areas 11 to 19 defined in a three rows by three columns matrix except for a center area 19. A first data bus 22a linearly extends between memory blocks in the first and second row of the matrix. A second data bus 22b linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: In a DRAM's word driver between the gate of a pulling-up p channel MOS transistor and that of a pulling-down, first n channel MOS transistor there is connected a second n channel MOS transistor having a gate receiving a power supply potential. Even when an input signal attains a high potential the first n channel MOS transistor has at its gate a potential equal to the power supply potential minus a threshold voltage of the second n channel MOS transistor. As such, the first n channel MOS transistor can receive at a gate insulating film thereof a voltage smaller than conventional. Thus the first n channel MOS transistor can operate more reliably.

Abstract: A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.

Abstract: In a DRAM's timing generator with a write-state signal generation circuit responding to activation of a write enable signal to activate a write-state signal and a write driver enable signal generation circuit responding to activation of the write-state signal to activate a write driver enable signal, there is provided a driver reset circuit responding to inactivation of a write enable signal to activate a driver reset signal applied to an NAND circuit downstream of a flip-flop circuit provided in a write driver enable signal generation circuit.

Abstract: A potential of an I/O line pair is defined at Vcc2−Vth by a clamp circuit, and a clamp voltage is generated by a current mirror circuit including an n channel MOS transistor and p channel MOS transistors and a constant current source. The I/O line pair is thus clamped through p channel MOS transistors connected in series between the I/O line pair.

Abstract: There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

Abstract: An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground potential Vss in a low level data output operation. The substrate potential of the pull up NMOS transistor is set to a potential of a level higher than the normal case in a high level data output operation. As a result, the output buffer can speedily charge the data terminal in a high level data output operation.

Abstract: In an output buffer of a DRAM, a level shifter outputs a step-up potential responsively when an internal data signal goes low or a test mode signature goes high. An N-channel MOS transistor is rendered conductive in response to the step-up potential from the level shifter, and sets a data input terminal to a power supply potential. The internal data signal and the test mode signature share the level shifter and the N-channel MOS transistor, and hence the layout area can be small and a high-level test mode signature can be output.

Abstract: A delay circuit includes a reference voltage generation circuit for generating a reference voltage which changes to a prescribed voltage level during the operation of a comparison circuit, an RC delay stage for integrating an input signal, a comparison circuit for comparing an output signal from the RC delay stage and the reference voltage of the reference voltage generation circuit, and a logic circuit for buffering the output signal of the comparison circuit. Since the reference voltage is pulled to a prescribed voltage level only during a comparison operation, the reference voltage may accurately be maintained at the prescribed voltage level only when necessary free from the influence of other circuits and noises. A delay circuit with reduced current consumption which is capable of changing an output signal with fixed delay time independently of the influence of fluctuations of the power supply voltage and the input logical threshold value of a logic circuit in a succeeding stage is provided.

Abstract: An SDRAM includes a test precharge signal generator which is activated in response to a test mode signal from a test mode detector. The test precharge signal generator generates a test precharge signal before generation of a precharge signal by a command decoder in response to a write signal from the command decoder. Therefore, in the wafer test using a clock signal having low frequency, it becomes possible to execute precharging operation before the input of the normal precharge command after the input of the write command. As a result, it becomes possible to replace a memory cell, which has low power in terms of write recovery time period, by a redundant memory cell in the wafer test, and to improve production yield.

Abstract: An output current of a constant current source formed of a gate potential control circuit and a p channel MOSFET is determined only by the sub threshold swing value of a p channel MOSFET and a resistance of a resistor. A signal out 1 controlling the operation of a ring oscillator circuit is switched at a predetermined potential corresponding to the sum of the threshold value of n channel MOSFETs through which the output current flows. Since the output current has no power supply voltage dependency and increases in proportion to the temperature, the predetermined potential is independent of the power voltage. The temperature dependency is also small since the temperature dependency of the output current value and the threshold value cancel each other. Therefore, the substrate potential can be controlled at a stable level unsusceptible to variation in the external operating conditions.

Abstract: In a DRAM, a bit-line potential inputting node of an equalizer provided for each odd-numbered pair of bit lines is provided separately from a bit-line potential inputting node of an equalizer provided for each even-numbered pair of bit lines. In burn-in testing, one node receives a high level and the other node receives a low level to simultaneously apply electric field stress between adjacent pairs of bit lines. This allows sufficient acceleration of initial failures in burn-in testing.