Abstract: An output transistor in an output buffer in a semiconductor memory device is formed in a well region which is electrically isolated from the substrate by a triple well structure. When the output transistor conducts, the potential of the well in which the output transistor is formed is controlled to follow the source potential of the output transistor, so that the increase in the threshold voltage caused by a substrate biasing effect can be prevented, and larger output current results.

Abstract: A main surface of a semiconductor substrate having the aspect ratio of 1:2 is equally divided into 9 regions of 3 rows and 3 columns, and a 2.sup.N-2 -bit subarray portion having the aspect ratio of 1:2 is arranged in each region other than a central region. The central region is provided with control circuitry and pads. Thus, a DRAM chip having the aspect ratio of 1:2 and the storage capacity of 2.sup.2N+1 bits can be formed. The DRAM chip can be contained at a high effective ratio in a package having the aspect ratio of 1:2 as is conventional.

Abstract: A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.

Abstract: An input signal applied to a terminal receiving an external signal (e.g. a data input/output terminal DQj) is transmitted by an input signal line. A p well formed in a main surface of a p substrate is electrically isolated from the p substrate by an n well and a triple n well. The p well and the n well receive a potential level of the signal input line. An n diffusion layer is formed in a main surface of the p well and receives an external power supply potential Vdd.

Abstract: A switching circuit for switching a bit line potential VBL of a DRAM to a power supply potential Vcc, an intermediate potential Vcc/2 or the ground potential GND is provided. In normal operation, the bit line potential VBL is set to Vcc/2. In a special write mode, Vcc or GND is applied to all the bit lines through an equalizer, a desired word line is raised to "H" level, and Vcc or GND is written to the storage nodes of all the memory cells connected to the word line. It is possible to write Vcc or GND even to the storage node of a memory cell which has been replaced by a redundant memory cell.

Abstract: An inhibition signal CAIHT for inhibiting, in adaptation to the data output timing of an output buffer, an internal column address strobe signal int/CAS output from a CAS buffer from falling from an H level to an L level for a prescribed period is generated and then applied to the CAS buffer. During data output, the internal column address strobe signal int/CAS is inhibited from being brought into an active state for the prescribed period, so that new data can be prevented from being transferred to the output buffer during this inhibition period, whereby erroneous data resulting from output noise can be prevented from being output. Consequently, a semiconductor memory device capable of correctly outputting data without the influence of the output noise is provided.

Abstract: In an address transition detecting circuit, signal conversion detecting circuits output complementary time difference signals which are inverted in response to potential level changes of corresponding address lines respectively. Waveform shaping one-shot pulse generating circuits receive corresponding complementary time difference signals and output one-shot pulse signals of prescribed time widths. A waveform composing circuit outputs an ATD signal of a prescribed pulse length in response to activation of any one-shot pulse signal. Therefore, the lengths of the one-shot pulses outputted from the waveform shaping one-shot pulse generating circuits remain unchanged even if the potential level of any signal line is abruptly converted, and an ATD signal of a constant pulse length is regularly outputted.

Abstract: P channel MOS transistors P11 and P12 have their gates cross-connected to their drains. P channel MOS transistors P13 and P14 each having its gate and its drain diode-connected to each other are respectively connected in parallel to transistors P11 and P12. N channel MOS transistors N15 and N16 drive transistors P11 to P14 with current values corresponding to input signals IN and /IN. If transistors P11-P14 have the same gate length, transistors P11 and P12 have the same gate width, and transistors P13 and P14 have the same gate width, the DC amplification factor of an internal differential amplifying circuit 1100 of a first stage can be set to a desired value by the ratio of a gate width of P13 to a gate width of P11. Internal outputs from nodes to which the drains of P11 and P12 are respectively connected are input to an internal differential amplifying circuit 1200 of the following stage.

Abstract: A semiconductor memory device includes four memory cell arrays, four output pads formed in a linear manner at the center of a semiconductor substrate, four output control circuits for generating readout data signals and control signals, four signal generation circuits responsive to the readout data signals for generating complementary pairs of data signals, and responsive to the control signals, four signal line groups including four signal lines connected between the output control circuits and the signal generation circuits, four output drivers responsive to pairs of data signals for supplying data to the output pads, and four signal line pairs connected between the signal generation circuits and output drivers. Signal generation circuits of great size are arranged at the center of the semiconductor substrate where the layout margin is great, and only the output driver is arranged in the proximity of the output pad where the layout margin is small. Therefore, the chip area is reduced.

Abstract: A semiconductor memory device includes a memory cell array, a redundant row memory cell array, a redundant column memory cell array and a redundant column row memory cell array. A redundant row test activation signal, a redundant column test activation signal and a multi-bit test activation signal are activated in response to signals RAS, CAS and WE and address key signals. In a redundant row test mode, a redundant word line is selectively driven in response to a row address signal. In a row column test mode, a redundant column selection line is selectively driven in response to a column address signal. In addition, data shrinking circuit is provided in order to enable a multi-bit test of redundant rows and redundant columns.

Abstract: A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

Abstract: When a pad is connected to ground and a mode switching signal MHYP attains an L level, an integrated semiconductor device attains an FP mode. Following the transition of an internal column address strobe signal ZCASF and an internal write enable signal ZWEF to an L level, an NOR gate is opened to allow entry of internal data. When the pad is connected to a power supply potential and the mode selecting signal MHYP attains an H level, the integrated semiconductor device attains an EDO mode. The NOR gate is opened when the internal row address strobe signal ZRASF attains an L level, whereby the external data is entered. The writing operation in an EDO mode can be increased in speed.

Abstract: A chip is divided into at least four regions of two rows and two columns. In each region, memory array blocks are provided between corresponding first control circuits disposed in the column direction at a constant pitch. A column decoder is disposed adjacent to the first control circuit. Second control circuits are disposed corresponding to the first control circuits. The second control circuits excluding the second control circuit on the column decoder side are formed in the same pattern.

Abstract: A charge pump circuit includes a P channel field effect transistor, a diode-connected N channel field effect transistor between a first node and a second node. The P channel field effect transistor operates in response to a first clock signal applied through a first capacitor to discharge the first node to a ground potential. The first node receives a second clock signal through a second capacitor. Negative electric charges are pumped out to the second node. A negative bias voltage is generated from the second node with an improved efficiency and reliability.

Abstract: A substrate is exposed to a gas of reactive material and an oxidizing gas. The oxidizing gas includes an ozone gas. A laser light beam is applied to the substrate through the reactive material gas and the oxidizing gas. The laser light beam activates the oxidizing gas. The activated oxidizing gas reacts with the reactive material gas to form an oxide deposited on the substrate.