Patents by Inventor Yasuhiro Fuwa
Yasuhiro Fuwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11400731Abstract: A thermal printhead includes a substrate having an obverse surface, a projection formed on the obverse surface and extending in a primary scanning direction, a plurality of heating elements arranged in the primary scanning direction on the top of the projection, a groove dented from the top of the projection and extending in the primary scanning direction, and a heat storage member filling at least an opening of the groove.Type: GrantFiled: June 5, 2020Date of Patent: August 2, 2022Assignee: ROHM CO., LTD.Inventors: Goro Nakatani, Masatoshi Nakanishi, Yasuhiro Fuwa
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Patent number: 11097554Abstract: A thermal printhead includes a substrate, a protrusion formed on an obverse surface of the substrate and extending in a main scanning direction, a heat storage layer formed on a top surface of the protrusion, and a plurality of heat-generating parts arranged along the main scanning direction on the heat storage layer. The substrate and the protrusion are integrally formed from a single-crystal semiconductor.Type: GrantFiled: June 24, 2020Date of Patent: August 24, 2021Assignee: ROHM CO., LTD.Inventors: Goro Nakatani, Akira Fujita, Kazuya Nakakubo, Yasuhiro Fuwa
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Publication number: 20210001641Abstract: A thermal printhead includes a substrate, a protrusion formed on an obverse surface of the substrate and extending in a main scanning direction, a heat storage layer formed on a top surface of the protrusion, and a plurality of heat-generating parts arranged along the main scanning direction on the heat storage layer. The substrate and the protrusion are integrally formed from a single-crystal semiconductor.Type: ApplicationFiled: June 24, 2020Publication date: January 7, 2021Inventors: Goro NAKATANI, Akira FUJITA, Kazuya NAKAKUBO, Yasuhiro FUWA
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Publication number: 20200391518Abstract: A thermal printhead includes a substrate having an obverse surface, a projection formed on the obverse surface and extending in a primary scanning direction, a plurality of heating elements arranged in the primary scanning direction on the top of the projection, a groove dented from the top of the projection and extending in the primary scanning direction, and a heat storage member filling at least an opening of the groove.Type: ApplicationFiled: June 5, 2020Publication date: December 17, 2020Inventors: Goro NAKATANI, Masatoshi NAKANISHI, Yasuhiro FUWA
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Patent number: 10833145Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.Type: GrantFiled: January 17, 2019Date of Patent: November 10, 2020Assignee: ROHM CO., LTD.Inventors: Hiroshi Tamagawa, Yasuhiro Kondo, Yasuhiro Fuwa, Hiroyuki Okada, Eiji Nukaga, Katsuya Matsuura
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Patent number: 10804190Abstract: A multi-chip module includes a plurality of chip parts with each chip part having an electrode, a sealing resin for sealing the plurality of chip parts, and an external connection terminal secured to the sealing resin so as to be exposed from the outer surface of the sealing resin and electrically connected to the electrode of at least one of the chip parts.Type: GrantFiled: June 13, 2016Date of Patent: October 13, 2020Assignee: ROHM CO., LTD.Inventors: Mamoru Yamagami, Yasuhiro Fuwa, Hideaki Yanagida, Takafumi Okada
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Patent number: 10777360Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.Type: GrantFiled: April 16, 2019Date of Patent: September 15, 2020Assignee: ROHM CO., LTD.Inventors: Hiroyuki Okada, Yasuhiro Fuwa
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Publication number: 20190244763Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Applicant: ROHM CO., LTD.Inventors: Hiroyuki OKADA, Yasuhiro FUWA
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Patent number: 10354936Abstract: An electronic component includes a substrate having a principal surface, a chip arranged at the principal surface of the substrate, a sealing resin sealing the chip on the principal surface of the substrate, and a heat dissipation member formed on the sealing resin.Type: GrantFiled: July 11, 2017Date of Patent: July 16, 2019Assignee: ROHM CO., LTD.Inventors: Yusuke Harada, Yasuhiro Fuwa
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Patent number: 10304633Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.Type: GrantFiled: December 8, 2017Date of Patent: May 28, 2019Assignee: ROHM CO., LTD.Inventors: Hiroyuki Okada, Yasuhiro Fuwa
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Patent number: 10297468Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.Type: GrantFiled: January 31, 2018Date of Patent: May 21, 2019Assignee: ROHM CO., LTD.Inventors: Yuichi Nakao, Yasuhiro Fuwa
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Publication number: 20190148480Abstract: [Theme] A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.Type: ApplicationFiled: January 17, 2019Publication date: May 16, 2019Applicant: ROHM CO., LTD.Inventors: Hiroshi TAMAGAWA, Yasuhiro KONDO, Yasuhiro FUWA, Hiroyuki OKADA, Eiji NUKAGA, Katsuya MATSUURA
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Patent number: 10279597Abstract: A thermal print head includes a semiconductor substrate, a resistor layer with heat generating portions arranged in the main scanning direction, a wiring layer included in a conduction path for energizing the heat generating portions, and a protective layer covering the resistor layer and the wiring layer. The semiconductor substrate includes a projection protruding from the obverse surface of the substrate and elongated in the main scanning direction. The projection has first and second inclined side surfaces spaced apart from each other in the sub-scanning direction. The heat generating portions are arranged to overlap with the first inclined side surface of the projection as viewed in plan view.Type: GrantFiled: September 20, 2017Date of Patent: May 7, 2019Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Yasuhiro Fuwa
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Patent number: 10249514Abstract: A semiconductor device includes a semiconductor element, a substrate formed with a recess in a main surface, a conductive layer formed on the substrate and electrically connected to the semiconductor element, and a sealing resin covering the semiconductor element. The substrate is made of an electrically insulative synthetic resin. The recess has a bottom surface on which the semiconductor element is mounted, and an intermediate surface connected to the main surface and the bottom surface. The bottom surface is orthogonal to the thickness direction of the substrate. The intermediate surface is inclined with respect to the bottom surface.Type: GrantFiled: August 1, 2016Date of Patent: April 2, 2019Assignee: ROHM CO., LTD.Inventor: Yasuhiro Fuwa
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Patent number: 10224391Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.Type: GrantFiled: July 12, 2017Date of Patent: March 5, 2019Assignee: ROHM CO., LTD.Inventors: Hiroshi Tamagawa, Yasuhiro Kondo, Yasuhiro Fuwa, Hiroyuki Okada, Eiji Nukaga, Katsuya Matsuura
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Patent number: 10112824Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.Type: GrantFiled: April 19, 2016Date of Patent: October 30, 2018Assignee: ROHM CO., LTD.Inventors: Yuichi Nakao, Yasuhiro Fuwa
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Patent number: 10070530Abstract: An electronic component includes a substrate including a first principal surface, a second principal surface positioned on a side opposite to the first principal surface, a first side surface that connects the first principal surface and the second principal surface and that extends along a first direction, a second side surface that connects the first principal surface and the second principal surface and that extends along a second direction intersecting the first direction, and a corner portion that connects the first side surface and the second side surface and that has a curved surface curved outwardly, and a chip arranged at the first principal surface of the substrate.Type: GrantFiled: July 10, 2017Date of Patent: September 4, 2018Assignee: ROHM CO., LTD.Inventors: Motohiro Toyonaga, Yasuhiro Fuwa, Mamoru Yamagami, Isamu Nishimura
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Publication number: 20180174759Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.Type: ApplicationFiled: December 8, 2017Publication date: June 21, 2018Applicant: ROHM CO., LTD.Inventors: Hiroyuki OKADA, Yasuhiro FUWA
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Publication number: 20180158696Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.Type: ApplicationFiled: January 31, 2018Publication date: June 7, 2018Inventors: Yuichi NAKAO, Yasuhiro FUWA
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Patent number: 9983272Abstract: Provided is a magnetism detection device by which it is possible to achieve a reduction in size and an increase in accuracy. A magnetism detection device includes: a magneto-impedance element; a magnetic field direction changing body; and a substrate that is formed of a semiconductor material and has an element arrangement recessed portion bottom surface and a back surface that face mutually opposite sides in a thickness direction, and a through-hole that reaches the element arrangement recessed portion bottom surface and the back surface and has a cross-sectional dimension that increases toward the main surface starting from the element arrangement recessed portion bottom surface. The magneto-impedance element is mounted on the element arrangement recessed portion bottom surface, and the magnetic field direction changing body is accommodated in the through-hole.Type: GrantFiled: December 10, 2015Date of Patent: May 29, 2018Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Yasuhiro Fuwa