Abstract: A semiconductor device includes a semiconductor layer having an element region and a termination region located around the element region. The termination region includes a first breakdown voltage holding structure disposed in a first depth range of the semiconductor layer, and a second breakdown voltage holding structure disposed in a second depth range different from the first depth range of the semiconductor layer and arranged so as to face the first breakdown voltage holding structure in a depth direction of the semiconductor layer. At least one of the first breakdown voltage holding structure or the second breakdown voltage holding structure includes a RESURF layer. An electric field intensity distribution of the first breakdown voltage holding structure and an electric field intensity distribution of the second breakdown voltage holding structure have an opposite relationship of height from an inner peripheral side toward an outer peripheral side of the termination region.

Abstract: A semiconductor device has a semiconductor substrate that includes an element range and a peripheral range. The semiconductor substrate includes: a body region disposed within the element range; a p-type deep region that is disposed from the element range through the peripheral range, is distributed from an upper surface of the semiconductor substrate to a position deeper than a lower end of each gate trench, and involves end gate trench; and a p-type voltage resistance region that is disposed within the peripheral range, and is distributed from the upper surface to a position shallower than a lower end of the p-type deep region. A p-type impurity concentration within the p-type deep region is increased in the direction from the body region toward the p-type voltage resistance region.

Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode and a lower electrode. The semiconductor substrate may include: a p-type anode region being in contact with the upper electrode; an n-type cathode region being in contact with the lower electrode; an n-type drift region interposed between the anode region and the cathode region. The semiconductor substrate may further include a barrier region interposed between the anode region and the drift region; and an n-type pillar region extending between the barrier region and the upper electrode. The barrier region may include a multi-layer structure in which a p-type second barrier layer is interposed between an n-type first barrier layer and an n-type third barrier layer. The first barrier layer may be in contact with the anode region and is connected to the upper electrode via the pillar region.

Abstract: A semiconductor device has a semiconductor substrate that includes an element range and a peripheral range. The semiconductor substrate includes: a body region disposed within the element range; a p-type deep region that is disposed from the element range through the peripheral range, is distributed from an upper surface of the semiconductor substrate to a position deeper than a lower end of each gate trench, and involves end gate trench; and a p-type voltage resistance region that is disposed within the peripheral range, and is distributed from the upper surface to a position shallower than a lower end of the p-type deep region. A p-type impurity concentration within the p-type deep region is increased in the direction from the body region toward the p-type voltage resistance region.

Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode and a lower electrode. The semiconductor substrate may include: a p-type anode region being in contact with the upper electrode; an n-type cathode region being in contact with the lower electrode; an n-type drift region interposed between the anode region and the cathode region. The semiconductor substrate may further include a barrier region interposed between the anode region and the drift region; and an n-type pillar region extending between the barrier region and the upper electrode. The barrier region may include a multi-layer structure in which a p-type second barrier layer is interposed between an n-type first barrier layer and an n-type third barrier layer. The first barrier layer may be in contact with the anode region and is connected to the upper electrode via the pillar region.

Abstract: A semiconductor device includes a semiconductor substrate including, on a first surface, first trenches and a second trench linked to each of the first trenches. The semiconductor substrate includes: a p-type end layer extending from the first surface to a position closer to a second surface of the semiconductor substrate than an end of each of the first trenches on a second surface side and including a longitudinal end of each of the first trenches in a plan view of the first surface; a first p-type layer provided in a region between adjacent first trenches, and contacting the first electrode provided on the first surface; an n-type barrier layer; a second p-type layer. The second trench separates the p-type end layer from the first p-type layer and the second p-type layer.

Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

Abstract: A semiconductor device includes a semiconductor substrate including, on a first surface, first trenches and a second trench linked to each of the first trenches. The semiconductor substrate includes: a p-type end layer extending from the first surface to a position closer to a second surface of the semiconductor substrate than an end of each of the first trenches on a second surface side and including a longitudinal end of each of the first trenches in a plan view of the first surface; a first p-type layer provided in a region between adjacent first trenches, and contacting the first electrode provided on the first surface; an n-type barrier layer; a second p-type layer. The second trench separates the p-type end layer from the first p-type layer and the second p-type layer.

Abstract: A semiconductor device for restraining snapback is provided. The semiconductor device includes IGBT and diode regions. In a view of n-type impurity concentration distribution along a direction from a front surface to a rear surface, a local minimum value of an n-type impurity concentration is located at a border between cathode and buffer regions. A local maximum value of n-type impurity concentration is located in the buffer region. At least one of the buffer and cathode regions includes a crystal defect region having crystal defects in a higher concentration than a region therearound. A peak of a crystal defect concentration in a view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value.

Abstract: A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.

Abstract: A semiconductor device for restraining snapback is provided. The semiconductor device includes IGBT and diode regions. In a view of n-type impurity concentration distribution along a direction from a front surface to a rear surface, a local minimum value of an n-type impurity concentration is located at a border between cathode and buffer regions. A local maximum value of n-type impurity concentration is located in the buffer region. At least one of the butler and cathode regions includes a crystal defect region having crystal detects in a higher concentration than a region therearound. A peak of a crystal defect concentration in a view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value.

Abstract: An IGBT comprises emitter regions, a collector region, a drift region and a body region in a semiconductor substrate. The semiconductor substrate comprises a trench extending from the front surface of the semiconductor substrate and reaching the drill region. The trench partitions the front surface of the semiconductor substrate into a plurality of blocks in a plan view of the semiconductor substrate. The plurality of the blocks comprises cell blocks, each of which is partitioned to be smaller than a predetermined area by the trench, and a surrounding block which is a region other than the cell blocks. The collector region, the drift region, the body region and the emitter region are provided in each of the cell blocks and the surrounding block. A total area of the emitter regions in the cell blocks is greater than a total area of the emitter region in the surrounding block.

Abstract: A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a second conductive type that is disposed above the drift region, and a barrier region of the first conductive type that is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region is not contact with a side surface of the insulated trench gate.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the barrier region is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region includes a first barrier partial region, wherein a distance between the first barrier partial region and the drift region is a first distance, and a second barrier partial region, wherein a distance between the second barrier partial region and the drift region is a second distance which is longer than the first distance. The second barrier partial region is in contact with a side surface of an insulated trench gate.

Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

Abstract: A buffer layer includes an n+-type first buffer region and an n+-type second buffer region. The first buffer region is provided at a first depth from a first main surface of a semiconductor layer and has an impurity concentration higher than an impurity concentration of a drift layer. The second buffer region is provided at a second depth from the first main surface of the semiconductor layer and has an impurity concentration higher than the impurity concentration in the drift layer, the second depth being shallower than the first depth. The first buffer region delimits an opening in a plane of the semiconductor layer at the first depth. The second buffer region delimits an opening in a plane of the semiconductor layer at the second depth.

Abstract: A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.