Abstract: A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.

Abstract: A semiconductor device which can suppress the influence of the external electric charge and can be efficiently manufactured is provided. The semiconductor device is provided with an active region in which a semiconductor element is disposed and a termination region between the active region and an edge surface of the semiconductor substrate. An insulating layer is disposed on at least a part of an upper surface of the termination region. A plurality of floating electrodes is disposed at an interval in the insulating layer in a direction from the active region toward the edge surface of the semiconductor substrate, and a width of the plurality of floating electrodes in a thickness direction of the semiconductor substrate is greater than a width of the plurality of floating electrodes in the direction from the active region toward the edge surface of the semiconductor substrate.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a second conductive type that is disposed above the drift region, and a barrier region of the first conductive type that is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region is not contact with a side surface of the insulated trench gate.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the barrier region is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region includes a first barrier partial region, wherein a distance between the first barrier partial region and the drift region is a first distance, and a second barrier partial region, wherein a distance between the second barrier partial region and the drift region is a second distance which is longer than the first distance. The second barrier partial region is in contact with a side surface of an insulated trench gate.

Abstract: A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.

Abstract: A semiconductor device includes a semiconductor substrate. Dummy trenches and a grid-structured gate trench located between the dummy trenches are provided in the front surface. An emitter region, a first anode region, a first barrier region, and a first pillar region are provided in a cell region surrounded by the grid-structured gate trench. A drift region, a collector region, and a cathode region are provided in the semiconductor substrate. The first barrier region is an n-type region being in contact with a gate insulating film at a position on the rear surface side of the first anode region. The first pillar region is an n-type region extending along a thickness direction, being in contact with a front surface electrode, connected to the first barrier region, and separated from the gate insulating film.

Abstract: By using an SOI substrate in which a front surface-side semiconductor layer, an insulating layer, and a back surface-side semiconductor layer are laminated in this order, vertical semiconductor devices are mass-produced. A process to be executed on a front surface of the SOI substrate is executed on the front surface. A back surface of the SOI substrate is etched so that the back surface-side semiconductor layer and the insulating layer are removed and a back surface of the front surface-side semiconductor layer is exposed. A process to be executed on the exposed back surface of the front surface-side semiconductor layer is executed on the back surface. A thickness of the front surface-side semiconductor layer of the SOI substrate can be accurately controlled, and the semiconductor devices having a semiconductor layer with the same thickness as the thickness of the front surface-side semiconductor layer are mass-produced.

Abstract: A semiconductor device is provided with a silicon layer, an upper surface side aluminum layer containing silicon and an insulation film. The upper surface side aluminum layer contacts and is layered on a part of a surface of the silicon layer. The insulation film contacts and is layered on another part of the surface of the silicon layer. The insulation film is adjacent to and contacts the upper surface side aluminum layer. The insulation film includes an insulation film body and a plurality of first nodule segregated portions projecting from the insulation film body toward the upper surface side aluminum layer as seen along a vertical direction relative to the surface of the silicon layer. A corner is formed by a side surface of the insulation film body and a side surface of each of the first nodule segregated portions as seen along the vertical direction.

Abstract: A semiconductor device 1 in which an IGBT region 2 and a diode region 3 adjoining each other are formed on a same substrate 4 is presented. The semiconductor device 1 is provided with a plurality of first gate trenches 11 extending abreast in a first direction in the IGBT region 2 and a plurality of second gate trenches 12 extending abreast in a second direction intersecting the first direction. The first gate trenches 11 and the second gate trenches 12 are not in contact with each other.

Abstract: A semiconductor device disclosed herein includes an insulated gate, a main and a sub trench conductors. The main and sub trench conductors are formed in the cell region, and have a conductor that is covered with an insulation film and fills a trench extending in a first direction. The sub trench is located, with respect to the main trench conductor, in a second direction perpendicularly crossing the first direction and extending from the cell region side to the non-cell region. Length of the sub trench conductor in the first direction is shorter than a length of the insulated gate in the first direction. Distance between the main and sub trench conductors is shorter than a distance between the main trench conductor and the insulated gate. At least a part of the sub trench conductor reaches a position deeper than a boundary between the first and second semiconductor regions.

Abstract: A semiconductor device which can suppress the influence of the external electric charge and can be efficiently manufactured is provided. The semiconductor device is provided with an active region in which a semiconductor element is disposed and a termination region between the active region and an edge surface of the semiconductor substrate. An insulating layer is disposed on at least a part of an upper surface of the termination region. A plurality of floating electrodes is disposed at an interval in the insulating layer in a direction from the active region toward the edge surface of the semiconductor substrate, and a width of the plurality of floating electrodes in a thickness direction of the semiconductor substrate is greater than a width of the plurality of floating electrodes in the direction from the active region toward the edge surface of the semiconductor substrate.

Abstract: A semiconductor device disclosed herein includes an insulated gate, a main and a sub trench conductors. The main and sub trench conductors are formed in the cell region, and have a conductor that is covered with an insulation film and fills a trench extending in a first direction. The sub trench is located, with respect to the main trench conductor, in a second direction perpendicularly crossing the first direction and extending from the cell region side to the non-cell region. Length of the sub trench conductor in the first direction is shorter than a length of the insulated gate in the first direction. Distance between the main and sub trench conductors is shorter than a distance between the main trench conductor and the insulated gate. At least a part of the sub trench conductor reaches a position deeper than a boundary between the first and second semiconductor regions.