Abstract: A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each processing node for storing in parallel use status information indicating whether the resource is in exclusive use status. The computer system includes a plurality of request issue circuits, each being provided in each processing node, for issuing requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to the processing nodes and a plurality of status control circuits. Each status control circuit is provided in each processing node to update a corresponding register set depending on use status information and each request received at a corresponding node.

Abstract: A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits.

Abstract: A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.

Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Abstract: In order to reduce load at a resource managing node for exclusive control of a shared resource, each node has a group of lock state registers each corresponding to one of the nodes. Before one node issues a lock request to a resource managing node, the node checks the register group to see if the resource managing node is unlocked. With the target node found to be accessible, the access requesting node sends to a broadcast message exchange circuit a broadcast request message including a lock request regarding the resource managing node. The broadcast message exchange circuit receives such broadcast request messages from access requesting nodes, and changes them serially into broadcast messages for broadcast to all nodes. Of these broadcast messages, the first message received by each node is processed by its lock control circuit so that the lock request in that message is allowed to lock the resource managing node.

Abstract: A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program.

Abstract: In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Abstract: A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

Abstract: The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register.

Abstract: A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.

Abstract: In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.

Abstract: Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching information for synchronization written into a main storage. When one program being executed by one of the processors issues an instruction, the circuit fetches information for synchronization from a location within the main storage designated by the instruction, compares that fetched information with another information designated by the instruction. If they do not have a specific relation, the fetching and the comparison is repeated. The circuit has a circuit for limiting the repetition with a limited number of times. The circuit further has a circuit for counting a total amount of CPU time spent for execution of plural watching instructions issued by the same program.

Abstract: An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.

Abstract: A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.

Abstract: A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder.

Abstract: A plurality of electric data signals representing parallel data bits are applied to a plurality of gates or control terminals on-off controlling optical switches, respectively. A single pulsed synchronizing signal is distributed to input terminals of the plurality of gates or the optical switches. Synchronizing signals, which have passed through gates or optical switches, which are in an ON state, among the plurality of gates or the optical switches are coupled to synchronize finally an optical signal. In this way a serial optical pulsed output signal can be obtained by utilizing optical delay in a process for distributing the synchronizing signals or a process for coupling the synchronizing signals.

Abstract: A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage device. The tightly coupled multiprocessors are connected with each other through a shared extended storage device. A compiler or preprocessor for the system analyzes the data to be allocated on the extended storage devices so that large scaled data accessed from each tightly-coupled multiprocessor are allocated on the local extended storage whereas the data to be accessed from a plurality of tightly-coupled multiprocessors are allocated on the shared extended storage.

Abstract: In a processor system for executing a plurality of tasks, which respectively control execution of one or more of a plurality of processes, a method of restarting execution of a first process which is under control of a specific task being executed, after the first process is stopped to wait for occurrence of an event associated with at least one second process different from the first process, includes the steps of (a) detecting whether or not the event associated with the second process has occurred; (b) restarting the execution of the first process when it is detected that the event has occurred; (c) determining whether or not there is an execution waiting process when the event has not yet occurred; (d) executing an executing waiting process when there is any; and (e) repeating the steps (a) to (d) after execution of an execution waiting process when there is any or after the step (c) when there is not such an execution waiting process.

Abstract: At least one common vector register capable of being accessed from a plurality of vector processors constituting the multiprocessor is provided in order to transfer vector data among the vector processors at a high speed. The common vector register includes data fields each holding the value of vector data, access control sections provided corresponding to the respective data fields and showing the status of data access from the vector processor for synchronization of data sending and receiving, when the vector data is transferred among the different vector processors through the common vector register, and an access right section used for managing the number of the vector processor which is allowed to access the common vector register.

Abstract: A vector processing apparatus includes a vector processing unit having a vector instruction decoder and a scalar processing unit including a scalar instruction decoder for activating the vector processing unit in response to a scalar instruction commanding initiation of the processing of a vector instruction chain. The vector processing unit further includes an incidation register which is set in response to the initiation of decodiung of the vector instruction chain by the vector instruction decoder and reset in response to the decoding of an end vector instruction of the vector instruction chain. So long as the indication circuit is in the reset state, the vector processing unit is allowed to initiate the processing of a vector instruction chain under the command of the scaler processing unit.