Abstract: In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address translation sizes is prepared; the logical address designated by the program is fetched; an entry of an address translation table whose address translation size is larger than those of the other address translation tables among the plurality of address translation sizes is first identified based on the fetched logical address; a first information on an address translation size validity included in the first indentified entry is checked; address translation in units of translation size of the address translation table including the first identified entry is performed when the first information indicates valid; when the first information indicates invalid, an entry of an address translation table whose address translation size is next smaller than that of the address translation table including the first identified entry

Abstract: In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided.

Abstract: A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register.

Abstract: A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

Abstract: A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state.

Abstract: In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.

Abstract: A unit operative in concurrence with a vector processing for beforehand sequentially generating page addresses containing vector data to be referred to thereafter and a unit for achieving a processing to determine whether or not a page fault occurs in a page in an address translation and responsive to an occurrence of a page fault in a page for executing processing to beforehand transfer the page to a main storage are provided. Even if a vector element existing in the page becomes necessary in the vector processing after the operation described above, another paging processing is not necessary because the page exists in the main storage.

Abstract: A vector instruction which designates calculation of vector data or vector data transfer between vector registers and the main memory, is arranged in such a way as to specify an element in the vector register from which the read/write operation is to be commenced, in order to make it possible to start the reading or writing of the vector data stored in the vector register from any desired element, thereby allowing a partial reference to the array data to be made on the vector register. Further, a vector instruction, which designates the vector data transfer between each vector register and the main memory, is arranged in such a way as to be able to specify the number of vector data elements to be transferred, thereby allowing transfer of elements requisite and adequate for a plurality of partial references on the vector register.

Abstract: A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.

Abstract: In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.

Abstract: An approximate quotient-correcting circuit wherein an approximate quotient Q.sub.H, a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q.sub.H and the divisor D are multiplied; it is decided whether the lower m digits of Q.sub.H .times.D are not all `0` and whether the m-th significant bit of Q.sub.H .times.D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q.sub.H -2.sup.-m is provided as a quotient.