Patents by Inventor Yasuhiro Isobe

Yasuhiro Isobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12273101
    Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: April 8, 2025
    Assignees: Kabusbiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toru Sugiyama, Noriaki Yoshikawa, Yasuhiko Kuriyama, Akira Yoshioka, Hitoshi Kobayashi, Hung Hung, Yasuhiro Isobe, Tetsuya Ohno, Hideki Sekiguchi, Masaaki Onomura
  • Patent number: 12170316
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Grant
    Filed: October 20, 2023
    Date of Patent: December 17, 2024
    Assignees: Kabushika Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Yasuhiro Isobe, Hung Hung, Hitoshi Kobayashi, Tetsuya Ohno, Toru Sugiyama
  • Publication number: 20240322027
    Abstract: A conductor layer is positioned between a gate electrode and a drain electrode. The conductor layer contacts a nitride semiconductor layer. The conductor layer is electrically connected with the drain electrode. The drain electrode includes a first part contacting the nitride semiconductor layer, and a second part positioned further toward the conductor layer side than the first part in a first direction. An insulating film includes a portion positioned between the conductor layer and the drain electrode. The second part is located on the portion of the insulating film.
    Type: Application
    Filed: August 23, 2023
    Publication date: September 26, 2024
    Inventors: Hitoshi KOBAYASHI, Masaaki ONOMURA, Toru SUGIYAMA, Akira YOSHIOKA, Yasuhiro ISOBE, Tetsuya OHNO, Hideki SEKIGUCHI, Hung HUNG, Yorito KAKIUCHI
  • Publication number: 20240321974
    Abstract: A semiconductor device includes first and second semiconductor layers, first to third electrodes, an insulating region and a conductive layer. The second semiconductor layer is located on the first semiconductor layer. The first electrode is located on the second semiconductor layer. The second electrode is located on the second semiconductor layer and arranged with the first electrode in a second direction. The third electrode is positioned between the first electrode and the second electrode. The insulating region is located on the second semiconductor layer. The insulating region is between the first electrode and the second electrode and next to the first electrode. The insulating region includes first and second insulating portions. The second insulating portion is positioned above the first insulating portion. The conductive layer is located between the first insulating portion and the second insulating portion. The conductive layer is electrically connected with the first electrode.
    Type: Application
    Filed: August 28, 2023
    Publication date: September 26, 2024
    Inventors: Hideki SEKIGUCHI, Akira YOSHIOKA, Toru SUGIYAMA, Yasuhiro ISOBE
  • Publication number: 20240321977
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a conductive part, an insulating part, and a third electrode. The second semiconductor layer is located on the first semiconductor layer. The first electrode is located on the second semiconductor layer. The first electrode includes an electrode part and an electrode extension part. The electrode part contacts the second semiconductor layer. The electrode extension part extends from an upper end portion of the electrode part. The conductive part is positioned between the first electrode and the second electrode. The conductive part contacts an upper surface of the second semiconductor layer and contacting the first electrode. The insulating part is located on the conductive part and is positioned between the conductive part and the electrode extension part.
    Type: Application
    Filed: August 25, 2023
    Publication date: September 26, 2024
    Inventors: Akira YOSHIOKA, Hitoshi KOBAYASHI, Hideki SEKIGUCHI, Hung HUNG, Yasuhiro ISOBE, Toru SUGIYAMA
  • Patent number: 12062651
    Abstract: A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 13, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yasuhiro Isobe, Hung Hung, Akira Yoshioka, Toru Sugiyama, Hitoshi Kobayashi, Tetsuya Ohno, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura
  • Patent number: 12046668
    Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: July 23, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toru Sugiyama, Akira Yoshioka, Hitoshi Kobayashi, Masaaki Onomura, Yasuhiro Isobe, Hung Hung, Hideki Sekiguchi, Tetsuya Ohno
  • Patent number: 12027614
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer including an element region and an element isolation region; a first insulation film provided on the semiconductor layer; a first electrode provided on the first insulation film and extending in a first direction; a second electrode provided on the semiconductor layer, arranged in a second direction intersecting with the first direction, and extending in the first direction; a third electrode provided on the semiconductor layer, arranged in the second direction, and extending in the first direction; second insulation films provided between the first insulation film and the semiconductor layer, and interposing the third electrode in the second direction; a first field plate electrode provided on the first electrode and connected to the first electrode; a second field plate electrode provided on the first field plate electrode and connected to the second electrode; and a third field plate electrode provided on the third electrode and connec
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 2, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hitoshi Kobayashi, Yasuhiro Isobe, Hung Hung
  • Patent number: 12002858
    Abstract: A semiconductor device has a first and a second nitride semiconductor layer and a first and a second electrode thereon. A gate electrode is between the first and second electrodes. A gate field plate is on the gate electrode. A first field plate is above a position between the gate field plate and the second electrode. A second field plate is between the first field plate and the gate field plate. A distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to the portion of the gate field plate that protrudes the most towards the second electrode. The distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to an end surface of the first field plate on a first electrode side.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: June 4, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tetsuya Ohno, Akira Yoshioka, Toru Sugiyama, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi
  • Patent number: 11984387
    Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 14, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toru Sugiyama, Akira Yoshioka, Yasuhiro Isobe
  • Patent number: 11948864
    Abstract: A semiconductor device has a first wiring extending in a first direction on a nitride semiconductor layer. A source electrode is electrically connected to the first wiring and extends in a second direction. A drain electrode extends in the second direction and includes a first and second portion extending in the second direction, spaced from each other in the first direction. An element isolation region is in the second nitride semiconductor layer between the first and second portions. A third portion extends in the second direction on the first and second portions. A gate electrode extends in the second direction on the second nitride semiconductor layer between the source electrode and the drain electrode. The portion includes holes therein aligned with each other along the second direction with the spacing between adjacent holes in the second direction increasing with increasing distance in the second direction from the first wiring.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: April 2, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Toru Sugiyama, Hitoshi Kobayashi
  • Publication number: 20240105826
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film. A lower end of the first field plate electrode is located on a second surface of the first electrode film, the second surface being in contact with the second electrode film, rather than a first surface of the first electrode film, the first surface being in contact with the first insulating film.
    Type: Application
    Filed: March 1, 2023
    Publication date: March 28, 2024
    Inventors: Hitoshi KOBAYASHI, Masaaki ONOMURA, Toru SUGIYAMA, Akira YOSHIOKA, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO, Yasuhiro ISOBE
  • Publication number: 20240105563
    Abstract: A semiconductor device includes a nitride semiconductor element, a first diode, and a second diode; the nitride semiconductor element includes a conductive mounting bed, a semiconductor substrate formed on the mounting bed, a first nitride semiconductor layer, a second nitride semiconductor layer, a first major electrode, a second major electrode, a first gate electrode, and a second gate electrode; the first diode includes a first anode electrode electrically connected to the mounting bed, and a first cathode electrode electrically connected to the first major electrode; and the second diode includes a second anode electrode electrically connected to the mounting bed, and a second cathode electrode electrically connected to the second major electrode.
    Type: Application
    Filed: March 9, 2023
    Publication date: March 28, 2024
    Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Hideki SEKIGUCHI, Tetsuya OHNO, Masaaki ONOMURA
  • Publication number: 20240097671
    Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 21, 2024
    Inventors: Toru SUGIYAMA, Noriaki YOSHIKAWA, Yasuhiko KURIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Hung HUNG, Yasuhiro ISOBE, Tetsuya OHNO, Hideki SEKIGUCHI, Masaaki ONOMURA
  • Publication number: 20240088280
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer having a heterojunction, a second semiconductor layer on the first semiconductor layer and having another heterojunction, a drain electrode on the second semiconductor layer, a source electrode provided on the first semiconductor layer, a gate electrode provided on the first semiconductor layer between the drain electrode and the source electrode, and a first insulating film between the gate electrode and the drain electrode covering the first semiconductor layer and the second semiconductor layer. The second semiconductor layer being separated from the gate electrode by a portion of the insulating film. A distance from the second semiconductor layer to the gate electrode is shorter than a distance from the drain electrode to the gate electrode.
    Type: Application
    Filed: February 28, 2023
    Publication date: March 14, 2024
    Inventors: Hung HUNG, Yasuhiro ISOBE, Akira YOSHIOKA, Toru SUGIYAMA, Hitoshi KOBAYASHI
  • Publication number: 20240047533
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Inventors: Akira YOSHIOKA, Yasuhiro ISOBE, Hung HUNG, Hitoshi KOBAYASHI, Tetsuya OHNO, Toru SUGIYAMA
  • Patent number: 11830916
    Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Yoshioka, Yasuhiro Isobe, Hung Hung, Hitoshi Kobayashi, Tetsuya Ohno, Toru Sugiyama
  • Publication number: 20230290871
    Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 14, 2023
    Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Hitoshi KOBAYASHI, Masaaki ONOMURA, Yasuhiro ISOBE, Hung HUNG, Hideki SEKIGUCHI, Tetsuya OHNO
  • Publication number: 20230081850
    Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.
    Type: Application
    Filed: March 3, 2022
    Publication date: March 16, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toru SUGIYAMA, Akira YOSHIOKA, Yasuhiro ISOBE
  • Publication number: 20230080613
    Abstract: A semiconductor device includes a first terminal, a second terminal, a first chip, and a resistance part. The first chip includes a substrate electrically connected to the second terminal, a nitride semiconductor layer located on the substrate, a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal, a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal, and a substrate capacitance between the first drain electrode and the substrate. The resistance part is connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal.
    Type: Application
    Filed: March 2, 2022
    Publication date: March 16, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toru Sugiyama, Akira Yoshioka, Hung Hung, Yasuhiro Isobe, Hitoshi Kobayashi