Patents by Inventor Yasuhiro Katsumata

Yasuhiro Katsumata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110179991
    Abstract: There is provided an indicator in which a moving member 9 on which a pointer 21 is installed is caused to run on a guide rail 1 formed along a scale formed on a dial, characterized in that the moving member 9 comprises a first support member 11 for pivotally supporting a plurality of pulleys 17 which are arranged along the guide rail 1 and a second support member 13 for pivotally supporting at least a pulley 17, and in that the plurality of pulleys 17 pivotally supported on the first support member 11 and the pulley 17 pivotally supported on the second support member 13 hold the guide rail 1 therebetween and the first support member 11 and the second support member 13 are assembled to each other so as to slide in an inter-axis direction of the plurality of pulleys 17 which are pivotally supported on the first support member 11 and the pulley 17 which is pivotally supported on the second support member 13, the indicator having further a spring member 15 for biasing the first support member 11 and the second su
    Type: Application
    Filed: October 2, 2009
    Publication date: July 28, 2011
    Applicant: YAZAKI CORPORATION
    Inventors: Yasuhiro Katsumata, Tomohiro Sugiyama, Masaaki Sano
  • Patent number: 7964283
    Abstract: The present invention provides a coating liquid including organic metal complexes represented by Chemical Formula 1. R1-R8 in Chemical Formula 1 is one of the followings (1)-(4): (1) a group represented by CnH2n+1 (aforementioned n is an integral number equal to or larger than 0); (2) a group represented by COOR9 (aforementioned R9 is a group represented by CmH2m+1, and aforementioned m is an integral number equal to or larger than 0); (3) a halogen atom; and (4) CN or NO2.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 21, 2011
    Assignee: Central Japan Railway Company
    Inventors: Christopher Cordonier, Tetsuya Shichi, Takafumi Numata, Kenichi Katsumata, Akimasa Nakamura, Yasuhiro Katsumata, Teruo Komine, Kenichirou Amemiya, Akira Fujishima
  • Publication number: 20100317512
    Abstract: Disclosed is a method for forming a photocatalyst thin film, which is characterized in that a photocatalyst thin film containing a niobium-alkali metal complex oxide is formed by forming and then firing a layer containing a niobia nanosheet on the surface of a base containing an alkali metal.
    Type: Application
    Filed: February 8, 2008
    Publication date: December 16, 2010
    Applicant: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Christopher Cordonier, Tetsuya Shichi, Kenichi Katsumata, Yasuhiro Katsumata, Akira Fujishima, Takafumi Numata, Takayoshi Sasaki
  • Publication number: 20100279149
    Abstract: Disclosed is a method for forming a photocatalyst thin film, which is characterized in that a photocatalyst thin film containing a niobium-alkali metal complex oxide is formed by forming and then firing a layer containing niobium on the surface of a base containing an alkali metal.
    Type: Application
    Filed: February 8, 2008
    Publication date: November 4, 2010
    Applicant: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Christopher Cordonier, Tetsuya Shichi, Kenichi Katsumata, Yasuhiro Katsumata, Akira Fujishima
  • Publication number: 20100062281
    Abstract: The present invention provides a technology related to a conductive film which is high in transparency, conductivity, and adhesiveness to a base plate. The present invention also provides a coating liquid including metal materials reacting with a ligand represented by Chemical Formula 1 and including indium (In), tin (Sn), or both thereof. Each of R21—R24 in the Chemical Formula 1 is one of the followings (1)-(11) and X11 and X12 is either hetero atoms or carboxylic acid.
    Type: Application
    Filed: January 31, 2007
    Publication date: March 11, 2010
    Applicant: Central Japan Railway Company
    Inventors: Christopher Cordonier, Tetsuya Shichi, Takafumi Numata, Kenichi Katsumata, Akimasa Nakamura, Yasuhiro Katsumata, Teruo Komine, Kenichirou Amemiya, Makoto Yamashita, Akira Fujishima
  • Publication number: 20090324963
    Abstract: A coating liquid including one or more of metal complexes selected from a metal complex A represented by Chemical Formula 1, a metal complex B represented by Chemical Formula 2, and a metal complex C represented by Chemical Formula 3. M in Chemical Formula 1, Chemical Formula 2 and Chemical Formula 3 represents a metal ion. Each of X1-X4 in Chemical Formula 1, Chemical Formula 2 and Chemical Formula 3 is one of O, NH, CO2 and S. Each of Y1-Y8 in Chemical Formula 1 and Y1-Y4 in Chemical Formula 3 is either CH or N. Each of Z1-Z3 in Chemical Formula 2 and Chemical Formula 3 and Z4-Z6 in Chemical Formula 2 is one selected from a group of O, NH and S, and two selected from a group of CH and N. L in Chemical Formula 1, Chemical Formula 2 and Chemical Formula 3 represents an axial ligand. k in Chemical Formula 1, Chemical Formula 2 and Chemical Formula 3 represents a valence of each of the metal complexes and is equal to a sum of electric charges of M, X1-X4 and L.
    Type: Application
    Filed: July 12, 2007
    Publication date: December 31, 2009
    Applicant: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Christopher Cordonier, Tetsuya Shichi, Takafumi Numata, Kenichi Katsumata, Akimasa Nakamura, Yasuhiro Katsumata, Teruo Komine, Kenichirou Amemiya, Akira Fujishima, Makoto Yamashita
  • Publication number: 20090169899
    Abstract: The present invention provides a coating liquid including organic metal complexes represented by Chemical Formula 1. R1-R8 in Chemical Formula 1 is one of the followings (1)-(4): (1) a group represented by CnH2n+1 (aforementioned n is an integral number equal to or larger than 0); (2) a group represented by COOR9 (aforementioned R9 is a group represented by CmH2m+1, and aforementioned m is an integral number equal to or larger than 0); (3) a halogen atom; and (4) CN or NO2.
    Type: Application
    Filed: December 15, 2006
    Publication date: July 2, 2009
    Applicant: Central Japan Railway Company
    Inventors: Christopher Cordonier, Tetsuya Shichi, Takafumi Numata, Kenichi Katsumata, Akimasa Nakamura, Yasuhiro Katsumata, Teruo Komine, Kenichirou Amemiya, Akira Fujishima
  • Publication number: 20090075094
    Abstract: The present invention provides a coating liquid including organic metal complexes represented by Chemical Formula 1. R1—R8 in Chemical Formula 1 is one of the followings (1)-(4): (1) a group represented by CnH2n+1 (aforementioned n is an integral number equal to or larger than 0); (2) a group represented by COOR9 (aforementioned R9 is a group represented by CmH2m+1, and aforementioned m is an integral number equal to or larger than 0); (3) a halogen atom; and (4) CN or NO2.
    Type: Application
    Filed: December 25, 2006
    Publication date: March 19, 2009
    Inventors: Christopher Cordonier, Tetsuya Shichi, Takafumi Numata, Kenichi Katsumata, Akimasa Nakamura, Yasuhiro Katsumata, Teruo Komine, Kenichirou Amemiya, Akira Fujishima
  • Publication number: 20050262954
    Abstract: A headlamp in which light source units are tilted about predetermined tilting center axes by means of an aiming mechanism interposed between a lamp body and the light source units. The aiming mechanism includes a tilting fulcrum (a ball and socket joint), aiming screws which are rotatably supported on the lamp body, and nut members which thread fit on the screws and mounted on the light source units movably in forward and backward in response to the rotations of the screws, so as to tilt the light source units about the tilting center axes. A leaf spring slide portion brought into elastic engagement with a guide groove is made of a polyacetal resin which is superior in resistance to wear. A nut member main body having a screw thread fitting portion is made of a nylon resin which is superior in resistance to heat. There is no permanent set on the slide portion and a slide contact surface does not wear, and no looseness is generated in the screw thread fitting portion of the nut member main body.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 1, 2005
    Inventors: Toyozo Eto, Yasuhiro Katsumata
  • Patent number: 6635952
    Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: October 21, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Shigeru Kawanaka, Yoshihiro Minami, Yasuhiro Katsumata
  • Publication number: 20020140115
    Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumi Inoh, Shigeru Kawanaka, Yoshihiro Minami, Yasuhiro Katsumata
  • Patent number: 5903027
    Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: May 11, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
  • Patent number: 5898203
    Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: April 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
  • Patent number: 5886395
    Abstract: To obtain both the highest possible maximum operating frequency f.sub.max and early voltage V.sub.A, a semiconductor device provided with a bipolar transistor including a collector region, a base region formed on the collector region, an emitter region formed in contact with the base region, a base leading electrode connected to the base region, and an emitter electrode connected to the emitter region, is characterized in that a ratio Q.sub.B /N.sub.c of base Gunmel number Q.sub.B to impurity concentration N.sub.C of the collector region of the bipolar transistor lies within a range from 0.2.times.10.sup.-3 cm to 2.5.times..sup.-3 cm.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Katsumata, Chihiro Yoshino, Kazumi Inoh
  • Patent number: 5766965
    Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: June 16, 1998
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
  • Patent number: 5698881
    Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
  • Patent number: 5637909
    Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.
    Type: Grant
    Filed: January 2, 1996
    Date of Patent: June 10, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Yasuhiro Katsumata, Hiroshi Iwai, Toshihiko Iinuma, Kazumi Inou, Mitsuhiko Kitagawa, Kouhei Morizuka, Akio Nakagawa, Ichiro Omura
  • Patent number: 5620908
    Abstract: A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter tha
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: April 15, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Yasuhiro Katsumata, Satoshi Matsuda, Chihiro Yoshino
  • Patent number: 5604374
    Abstract: A semiconductor device comprises a semiconductor substrate having a main surface, a first semiconductor region of a first conductive type, formed on the main surface of the semiconductor substrate, a surrounding of the first semiconductor region is buried with a first insulation film, a second semiconductor region of a second conductive type, formed on the first insulation film and the first semiconductor region, a second insulation film, formed on the second semiconductor region, an end portion of the second insulation film is positioned above the first insulation film, and having an opening at a central portion thereof to be positioned above the first semiconductor region, and a third semiconductor region of a first conductivity type formed on a surface of the second semiconductor region exposed through the opening of the second insulation film.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: February 18, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inou, Yasuhiro Katsumata
  • Patent number: 5510647
    Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: April 23, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Yasuhiro Katsumata, Hiroshi Iwai, Toshihiko Iinuma, Kazumi Inou, Mitsuhiko Kitagawa, Kouhei Morizuka, Akio Nakagawa, Ichiro Omura