Patents by Inventor Yasuhiro Katsumata

Yasuhiro Katsumata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5434440
    Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: July 18, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
  • Patent number: 5204276
    Abstract: In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Nobuyuki Itoh, Hiroyuki Nihira, Eiryo Tsukioka, Kenji Hirakawa, Shin-ichi Taka, Hideki Takada, Yasuhiro Katsumata, Toshio Yamaguchi
  • Patent number: 4782030
    Abstract: A laminated film made of a first insulating film and a second insulating film having a selectivity of etching condition to the first insulating film is selectively formed on a first conductivity type semiconductor substrate to use the substrate under the laminated film as a base and emitter active region forming region. The laminated film remains until an anisotropically dry etching step is finished to prevent the base and emitter active region from damaging due to an etching atmosphere at anisotropically dry etching time.
    Type: Grant
    Filed: July 7, 1987
    Date of Patent: November 1, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Katsumata, Takao Ito