Patents by Inventor Yasuhiro Murase

Yasuhiro Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145711
    Abstract: A capacitor that includes a substrate having a principal surface; a dielectric film on the principal surface of the substrate; and an electrode layer on the dielectric film. The substrate has a recess structure portion with at least one recess portion in a second region outside a first region where the electrode layer overlaps the dielectric layer when viewed in a plan view from a normal direction of the principal surface of the substrate, and the dielectric film is on the recess structure portion.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
  • Publication number: 20210284682
    Abstract: The object of the present invention is to provide a method for manufacturing an amino acid polymer more simply and efficiently compared to conventional methods for manufacturing amino acid polymers. The present invention provides a method for manufacturing an amino acid polymer with thioacid amino acids. Specifically, the manufacturing method of the present invention comprises (A) a step of preparing first and second thioacid amino acids, (B) a step of subjecting said first and second thioacid amino acids to an oxidation reaction to obtain an amino acid polymer linked by peptide bonds. The manufacturing method of the present invention is characterized in that it partially uses thioacid amino acids that do not possess a protecting group.
    Type: Application
    Filed: February 28, 2018
    Publication date: September 16, 2021
    Inventors: Yasuhiro Kajihara, Masayuki Izumi, Ryo Okamoto, Takuya Haraguchi, Takefumi Murase
  • Patent number: 10991509
    Abstract: A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 27, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
  • Publication number: 20210027950
    Abstract: A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
  • Publication number: 20210006151
    Abstract: A CR snubber element includes a first resistance part, a first capacitance part, a second resistance part, and a second capacitance part. The first capacitance part is connected in series to the first resistance part. The second resistance part is connected in series to the first resistance part and the first capacitance part and the second capacitance part is connected in parallel to the second resistance part. The CR snubber element is configured such that the second resistance part is disconnected when the first capacitance part is short-circuited.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
  • Patent number: 10879347
    Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 29, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
  • Publication number: 20200381181
    Abstract: A capacitor that includes a substrate having a main surface with at least one of a recess or a projection, a dielectric film extending along the at least one of the recess or the projection and having an equivalent oxide thickness of 600 nm or more, and a conductor film covering at least part of the dielectric film.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
  • Publication number: 20200286880
    Abstract: A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
  • Publication number: 20200273796
    Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a first resistance control layer on the first electrode, a wiring part on the first resistance control layer, and a second electrode opposing the second main surface of the semiconductor substrate. The first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
  • Publication number: 20200176614
    Abstract: A capacitor that includes an insulating base material having a first main surface and a second main surface facing each other, the insulating base material defining first and second trenches extending from the first main surface into the base material such that first trench and the second trench overlap each other; a first conductor in the first trench; a first external electrode on the first main surface of the base material and connected to the first conductor; a second conductor in the second trench; and a second external electrode on the second main surface of the base material and connected to the second conductor.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
  • Publication number: 20200066445
    Abstract: A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Hiroshi NAKAGAWA, Tomoyuki Ashimine, Yasuhiro Murase
  • Publication number: 20190378893
    Abstract: A capacitor that includes a substrate having a principal surface; a dielectric film on the principal surface of the substrate; and an electrode layer on the dielectric film. The substrate has a recess structure portion with at least one recess portion in a second region outside a first region where the electrode layer overlaps the dielectric layer when viewed in a plan view from a normal direction of the principal surface of the substrate, and the dielectric film is on the recess structure portion.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
  • Publication number: 20190348496
    Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
  • Publication number: 20180233590
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: March 16, 2018
    Publication date: August 16, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 9954087
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 9837518
    Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Murase
  • Publication number: 20160293746
    Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 6, 2016
    Applicant: Renesas Electronics Corporation
    Inventor: Yasuhiro MURASE
  • Patent number: 9401413
    Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: July 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Murase
  • Patent number: 9264468
    Abstract: A content receiving apparatus including a receiver receiving first contents from a broadcasting station, a temporary memory unit temporarily storing first contents-related information related to the first contents, a memory storing the first contents and storing, based on an input recording request, the first contents-related information; and the memory storing a plurality of second contents and a plurality of second contents-related information received from a server, the second contents-related information being related to the first contents, and displayable.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: February 16, 2016
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Kikkoji, Nozomu Okuzawa, Shinsuke Yamashita, Jun Moriya, Yasuhiro Murase
  • Publication number: 20140367743
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: August 27, 2014
    Publication date: December 18, 2014
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto