Patents by Inventor Yasuhiro Murase
Yasuhiro Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200176614Abstract: A capacitor that includes an insulating base material having a first main surface and a second main surface facing each other, the insulating base material defining first and second trenches extending from the first main surface into the base material such that first trench and the second trench overlap each other; a first conductor in the first trench; a first external electrode on the first main surface of the base material and connected to the first conductor; a second conductor in the second trench; and a second external electrode on the second main surface of the base material and connected to the second conductor.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Publication number: 20200066445Abstract: A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Inventors: Hiroshi NAKAGAWA, Tomoyuki Ashimine, Yasuhiro Murase
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Publication number: 20190378893Abstract: A capacitor that includes a substrate having a principal surface; a dielectric film on the principal surface of the substrate; and an electrode layer on the dielectric film. The substrate has a recess structure portion with at least one recess portion in a second region outside a first region where the electrode layer overlaps the dielectric layer when viewed in a plan view from a normal direction of the principal surface of the substrate, and the dielectric film is on the recess structure portion.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Publication number: 20190348496Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.Type: ApplicationFiled: July 25, 2019Publication date: November 14, 2019Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Publication number: 20180233590Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: March 16, 2018Publication date: August 16, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 9954087Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: August 27, 2014Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 9837518Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.Type: GrantFiled: June 22, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventor: Yasuhiro Murase
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Publication number: 20160293746Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.Type: ApplicationFiled: June 22, 2016Publication date: October 6, 2016Applicant: Renesas Electronics CorporationInventor: Yasuhiro MURASE
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Patent number: 9401413Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.Type: GrantFiled: February 28, 2014Date of Patent: July 26, 2016Assignee: Renesas Electronics CorporationInventor: Yasuhiro Murase
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Patent number: 9264468Abstract: A content receiving apparatus including a receiver receiving first contents from a broadcasting station, a temporary memory unit temporarily storing first contents-related information related to the first contents, a memory storing the first contents and storing, based on an input recording request, the first contents-related information; and the memory storing a plurality of second contents and a plurality of second contents-related information received from a server, the second contents-related information being related to the first contents, and displayable.Type: GrantFiled: May 18, 2004Date of Patent: February 16, 2016Assignee: SONY CORPORATIONInventors: Hiroyuki Kikkoji, Nozomu Okuzawa, Shinsuke Yamashita, Jun Moriya, Yasuhiro Murase
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Publication number: 20140367743Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8853666Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: October 25, 2006Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Publication number: 20140264441Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.Type: ApplicationFiled: February 28, 2014Publication date: September 18, 2014Applicant: Renesas Electronics CorporationInventor: Yasuhiro MURASE
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Patent number: 8578438Abstract: In a content supply system, content data is supplied from a content supply apparatus to a content playback apparatus via a network. The content playback apparatus includes a request device for requesting a recovery process; an obtaining device for obtaining a start-up file; and a download device for downloading the content data. The content supply apparatus includes a customer information management device for managing customer information; a notification device for notifying the recovery information to the content playback apparatus; a start-up file generation device for generating a start-up file; a storage device for storing the start-up file; a content data supply device for allowing the content data to be downloaded; and a license data supply device for allowing the license data to be downloaded.Type: GrantFiled: May 17, 2005Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Yasuhiro Murase, Takeshi Iwatsu, Noriyuki Sakoh
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Patent number: 8466495Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: May 10, 2012Date of Patent: June 18, 2013Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Patent number: 8271797Abstract: A user sets an apparatus name easily identified by the user to a terminal, transmits the apparatus name together with user identification information to a terminal management server for managing a terminal, and the terminal management server registers the apparatus name as associated with the user identification information, thereby allowing the terminal management server to uniquely identify each terminal based on the apparatus name associated with the user identification information. Furthermore, a user can easily identify an apparatus name, thereby realizing a service utilizing system capable of reducing the laborious procedure of operating the terminal management server, and easily identifying each terminal.Type: GrantFiled: May 18, 2004Date of Patent: September 18, 2012Assignee: Sony CorporationInventors: Satoshi Araki, Jun Moriya, Toshikazu Minoshima, Junichi Nakamura, Naoki Yuasa, Shinsuke Yamashita, Yasuhiro Murase
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Publication number: 20120217547Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: NEC CORPORATIONInventors: Yuji ANDO, Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Takashi INOUE, Yasuhiro MURASE, Kazuki OTA, Akio WAKEJIMA, Naotaka KURODA
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Patent number: 8234669Abstract: A data-processing method of receiving broadcast contents and content-related information related to the broadcast contents. The method includes setting a frequency for receiving the broadcast contents from the broadcast station, and recording frequency information corresponding to the set frequency. The method also includes transmitting request information including broadcast station ID identifying the broadcast station corresponding to the frequency information to a server.Type: GrantFiled: March 19, 2010Date of Patent: July 31, 2012Assignee: Sony CorporationInventors: Hiroyuki Kikkoji, Nozomu Okuzawa, Shinsuke Yamashita, Jun Moriya, Yasuhiro Murase
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Patent number: 8198652Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: March 29, 2007Date of Patent: June 12, 2012Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Patent number: 8185924Abstract: Request information 3 is transmitted from a transmission means 1a of a communication device 1 to a server 2. Then, related information 4a corresponding to the request information 3 and an identification code 4b are obtained and transmitted to the communication device 1 by a transmission means 2c. The related information 4a and identification code 4b are stored in a storage means 1c of the communication device 1. Thereafter, purchase request information 5a is transmitted to the server 2 by the transmission means 1a. This purchase request information 5a is added with an identification code 5b and user identification information 5c. Then, content data 6a corresponding to the purchase request information 5a and additional data 6b corresponding to the identification code 5b are transmitted to the communication device 1 by the transmission means 2c of the server 2.Type: GrantFiled: May 18, 2004Date of Patent: May 22, 2012Assignee: Sony CorporationInventors: Hiroyuki Kikkoji, Nozomu Okuzawa, Shinsuke Yamashita, Jun Moriya, Yasuhiro Murase