Patents by Inventor Yasuhiro Nasu

Yasuhiro Nasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10193101
    Abstract: An electronic device includes: a flexible substrate, a device portion supported on the flexible substrate, and a driver circuit portion; and a flexible tube having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa), wherein: the flexible tube forms a first seal structure and a second seal structure at both ends thereof, and has a sealed space therein; a part of the flexible substrate and the device portion are inside the sealed space; and a rest of the flexible substrate, other than the part, is outside the sealed space.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 29, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhiro Nasu, Noriko Watanabe, Yasumori Fukushima, Shinsuke Saida
  • Publication number: 20170110680
    Abstract: An electronic device includes: a flexible substrate, a device portion supported on the flexible substrate, and a driver circuit portion; and a flexible tube having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa), wherein: the flexible tube forms a first seal structure and a second seal structure at both ends thereof, and has a sealed space therein; a part of the flexible substrate and the device portion are inside the sealed space; and a rest of the flexible substrate, other than the part, is outside the sealed space.
    Type: Application
    Filed: March 24, 2015
    Publication date: April 20, 2017
    Inventors: Yasuhiro NASU, Noriko WATANABE, Yasumori FUKUSHIMA, Shinsuke SAIDA
  • Patent number: 9612486
    Abstract: A liquid crystal display device is provided that has favorable display characteristics in a display mode using a vertical electric field and a horizontal electric field. This liquid crystal display device includes a first substrate and a second substrate arranged facing each other, and a liquid crystal layer sandwiched between the first substrate and the second substrate. The liquid crystal layer has liquid crystal molecules having a negative dielectric anisotropy, and the first substrate has a plate-shaped first common electrode and a pixel electrode formed in a separate layer from the first common electrode with an insulating film therebetween. The pixel electrode has a comb-shaped structure, and the second substrate has a second common electrode with a liquid crystal orientation structure that is linear in a plan view.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 4, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidefumi Yoshida, Yosuke Iwata, Mitsuhiro Murata, Yasuhiro Nasu, Koichi Miyachi, Tsuyoshi Kamata
  • Patent number: 9575364
    Abstract: This liquid crystal display device (100) includes: a vertical alignment liquid crystal layer (30); first and second substrates (10, 20); first and second electrodes (11, 21) arranged on the first and second substrates to face the liquid crystal layer; and two photo-alignment films (12, 22). Each pixel region includes first and second liquid crystal domains, of which the reference alignment directions defined by the two photo-alignment films are a first direction and a second direction different from the first direction, respectively. The first electrode has a slit cut region (11R1), through which a slit (11s) has been cut to run substantially parallel to the reference alignment direction, in a part of a region allocated to each of the first and second liquid crystal domains. The width (W) of the slit is set so that when the highest grayscale voltage is applied to the first electrode, an effective applied voltage decreases by at least 0.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: February 21, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidefumi Yoshida, Tsuyoshi Kamada, Tsuyoshi Maeda, Mitsuhiro Murata, Yoji Yoshimura, Yuichiro Yamada, Kenji Okamoto, Yosuke Iwata, Yasuhiro Nasu, Akira Sakai, Masahiro Hasegawa
  • Publication number: 20150177571
    Abstract: A liquid crystal display device is provided that has favorable display characteristics in a display mode using a vertical electric field and a horizontal electric field. This liquid crystal display device includes a first substrate and a second substrate arranged facing each other, and a liquid crystal layer sandwiched between the first substrate and the second substrate. The liquid crystal layer has liquid crystal molecules having a negative dielectric anisotropy, and the first substrate has a plate-shaped first common electrode and a pixel electrode formed in a separate layer from the first common electrode with an insulating film therebetween. The pixel electrode has a comb-shaped structure, and the second substrate has a second common electrode with a liquid crystal orientation structure that is linear in a plan view.
    Type: Application
    Filed: June 6, 2013
    Publication date: June 25, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidefumi Yoshida, Yosuke Iwata, Mitsuhiro Murata, Yasuhiro Nasu, Koichi Miyachi, Tsuyoshi Kamata
  • Publication number: 20140253853
    Abstract: This liquid crystal display device (100) includes: a vertical alignment liquid crystal layer (30); first and second substrates (10, 20); first and second electrodes (11, 21) arranged on the first and second substrates to face the liquid crystal layer; and two photo-alignment films (12, 22). Each pixel region includes first and second liquid crystal domains, of which the reference alignment directions defined by the two photo-alignment films are a first direction and a second direction different from the first direction, respectively. The first electrode has a slit cut region (11R1), through which a slit (11s) has been cut to run substantially parallel to the reference alignment direction, in a part of a region allocated to each of the first and second liquid crystal domains. The width (W) of the slit is set so that when the highest grayscale voltage is applied to the first electrode, an effective applied voltage decreases by at least 0.
    Type: Application
    Filed: October 11, 2012
    Publication date: September 11, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidefumi Yoshida, Tsuyoshi Kamada, Tsuyoshi Maeda, Mitsuhiro Murata, Yoji Yoshimura, Yuichiro Yamada, Kenji Okamoto, Yosuke Iwata, Yasuhiro Nasu, Akira Sakai, Masahiro Hasegawa
  • Publication number: 20140016075
    Abstract: The present invention provides a liquid crystal display panel and a liquid crystal display apparatus that features sufficiently fast response and are excellent in transmittance performance. The liquid crystal display panel includes a first substrate, a second substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. Each of the first substrate and the second substrate includes electrodes. The electrodes of the second substrate include a pair of comb substrates and a planar electrode. The liquid crystal display panel is configured to align liquid crystal molecules in the liquid crystal layer in a direction horizontal to a substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate.
    Type: Application
    Filed: September 18, 2013
    Publication date: January 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yosuke IWATA, Mitsuhiro MURATA, Hiroaki ASAGI, Yasuhiro NASU, Hidefumi YOSHIDA
  • Publication number: 20140002762
    Abstract: A liquid crystal driving method and a liquid crystal display apparatus that achieve a sufficiently fast response, and a sufficiently high transmittance, and reduces transmittance greatly during black image displaying. The liquid crystal driving method includes performing a driving operation to cause a potential difference between a first pair of electrodes during a subframe period, a driving operation to cause a potential difference between a second pair of electrodes, and a driving operation to cause no difference between all the electrodes of the first pairs of electrodes and the second pair of electrodes.
    Type: Application
    Filed: March 9, 2012
    Publication date: January 2, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yosuke Iwata, Mitsuhiro Murata, Yasuhiro Nasu, Hidefumi Yoshida, Hiroaki Asagi
  • Publication number: 20130148066
    Abstract: A liquid crystal panel (2) comprises a liquid crystal layer (30) sandwiched between two substrates (10 and 20) and alignment films (15 and 22) in contact with a liquid crystal layer. The liquid crystal panel (2) is of a vertical alignment type which drives the liquid crystal layer (30) by a transverse electric field which is generated between an upper electrode (14) and an lower layer electrode (12). A polar anchoring strength of each of the alignment films (15 and 22) falls within a range from more than 5×10?6 J/m2 to not more than 1×10?4 J/m2.
    Type: Application
    Filed: July 15, 2011
    Publication date: June 13, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yosuke Iwata, Mitsuhiro Murata, Yasuhiro Nasu, Toshihiro Matsumoto
  • Patent number: 7342617
    Abstract: The present invention relates to a liquid crystal display provided with an electrostatic protection element and an object of the present invention is to provide the liquid crystal display provided with superior redundancy and at the same time a sufficient protection function against static electricity in which relatively low voltage generates for a long period of time.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 11, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshinori Tanaka, Tetsuya Fujikawa, Yasuhiro Nasu
  • Publication number: 20060101325
    Abstract: The invention relates to an active matrix type liquid crystal display device and its driving method and provides a liquid crystal display device capable of omitting frame memory in image averaging processing among pixels for improving the smoothness of display and its driving method. For example, by providing an accumulated-charge-averaging TFT circuit which executes averaging of accumulated charges of a sub-pixel among a plurality of sub-pixels constructed within a pixel and adjacent sub-pixels within pixels adjacent thereto, thereby realizing smoothing processing of the display image without using a frame memory.
    Type: Application
    Filed: March 22, 2005
    Publication date: May 11, 2006
    Inventors: Nobuo Sasaki, Susumu Okazaki, Yasuhiro Nasu, Yoji Nagase
  • Patent number: 6914643
    Abstract: The present invention relates to a liquid crystal display provided with an electrostatic protection element and an object of the present invention is to provide the liquid crystal display provided with superior redundancy and at the same time a sufficient protection function against static electricity in which relatively low voltage generates for a long period of time.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Display Technologies Corporation
    Inventors: Yoji Nagase, Yoshinori Tanaka, Tetsuya Fujikawa, Yasuhiro Nasu
  • Publication number: 20040027502
    Abstract: The present invention relates to a liquid crystal display provided with an electrostatic protection element and an object of the present invention is to provide the liquid crystal display provided with superior redundancy and at the same time a sufficient protection function against static electricity in which relatively low voltage generates for a long period of time.
    Type: Application
    Filed: June 24, 2003
    Publication date: February 12, 2004
    Applicant: Fujitsu Display Technologies Corporation
    Inventors: Yoshinori Tanaka, Tetsuya Fujikawa, Yasuhiro Nasu
  • Patent number: 5580796
    Abstract: A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 3, 1996
    Assignee: Fujitsu Limited
    Inventors: Hideaki Takizawa, Yasuhiro Nasu, Kazuhiro Watanabe, Shiro Hirota, Kazuo Nonaka, Seii Sato, Teiji Majima
  • Patent number: 5496752
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 5, 1996
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5496749
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal .portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 5, 1996
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5483082
    Abstract: A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: January 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Hideaki Takizawa, Yasuhiro Nasu, Kazuhiro Watanabe, Shiro Hirota, Kazuo Nonaka, Seii Sato, Teiji Majima
  • Patent number: 5462885
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: October 31, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5407845
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: April 18, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5374570
    Abstract: A method of manufacturing an active matrix display device, in which particular emphases are laid on the forming step of an insulation layer by the ALE method and the precedent and subsequent steps thereof, thereby insulation layer being anyone among gate insulation layer, inter-busline insulation layer, protection layer and auxiliary capacitor insulation layer comprised in the display device. The method of forming the insulation layer comprises the predetermined number of repeated cycles of the steps of subjecting a substrate to the vapor of a metal inorganic/organic compound, which can react with H.sub.2 O and/or O.sub.2 and form the metal oxide, under molecular flow condition for duration of depositing almost a single atomic layer, and next subjecting the surface of thus formed metal inorganic/organic compound layer to the H.sub.2 O vapor and/or O.sub.2 gas under molecular flow condition for duration of replacing the metal inorganic/organic compound layer to the metal oxide layer.
    Type: Grant
    Filed: August 19, 1993
    Date of Patent: December 20, 1994
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Kenji Okamoto, Jun-ichi Watanabe, Tetsuro Endo, Shinichi Soeda