LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY APPARATUS

- SHARP KABUSHIKI KAISHA

The present invention provides a liquid crystal display panel and a liquid crystal display apparatus that features sufficiently fast response and are excellent in transmittance performance. The liquid crystal display panel includes a first substrate, a second substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. Each of the first substrate and the second substrate includes electrodes. The electrodes of the second substrate include a pair of comb substrates and a planar electrode. The liquid crystal display panel is configured to align liquid crystal molecules in the liquid crystal layer in a direction horizontal to a substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate.

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Description
TECHNICAL FIELD

The present invention relates to liquid crystal display panels and liquid crystal display apparatuses. More in detail, the present invention relates a liquid crystal display panel and a liquid crystal display apparatus that include liquid crystal molecules that are aligned in a direction vertical to a substrate main surface during a no-voltage application period.

BACKGROUND ART

A liquid crystal display panel is constructed by sandwiching a liquid crystal display element between a pair of glass substrates, or the like. With its flat, light-weight, and low-power consumption design, the liquid crystal display panel finds a wide range of applications including a personal computer, a television, on-board apparatuses including a car navigation system, and a display of a mobile information terminal such as a cell phone. The liquid crystal display panel is now an indispensable tool for daily life and business. In these applications, liquid crystal display panels of a variety of modes related to electrode arrangements and substrate designs to change optical characteristics of a liquid crystal layer have been studied.

Display modes in widespread use today include a vertical alignment (VA) mode in which liquid crystal molecules having a negative dielectric anisotropy are vertically aligned with respect to the surface of a substrate, an in-plane switching (IPS) mode in which an in-plane electric field is applied to a liquid crystal layer with liquid crystal molecules having positive or negative dielectric anisotropy horizontally aligned with respect to the surface of a substrate, and a fringe field switching (FFS) mode.

For example, a liquid crystal display apparatus of the FFS driving is disclosed as a thin-film transistor liquid crystal display having fast response and wide-view angle features. The liquid-crystal display apparatus includes a first substrate having a first common electrode layer, a second substrate having a pixel electrode layer and a second common electrode layer, liquid crystals sandwiched between the first substrate and the second substrate, and means that generates an electric field between the first common electrode of the first substrate and each of the pixel electrode layer and the second common electrode layer of the second substrate in order to provide a fast response to a fast input data transfer speed and a wide-view angle to a viewer (See Patent Literature 1, for example).

Also disclosed is another liquid crystal apparatus that applies an in-plane electric field with a plurality of electrodes. The liquid crystal display apparatus includes a liquid crystal layer containing liquid crystal molecules having a positive dielectric anisotropy and sandwiched between a pair of opposed substrates. The liquid crystal display apparatus includes a first substrate and a second substrate as the opposed substrates. Each of the first substrate and the second substrate includes an electrode, and the electrodes are opposed to each other with the liquid crystal layer interposed therebetween and are configured to apply a vertical electric field on the liquid crystal layer. The second substrate includes a plurality of electrodes that apply an in-plane electric field to the liquid crystal layer (see Patent Literature 2, for example).

CITATION LIST Patent Literature

  • PTL 1: Japanese Unexamined Patent Application Publication No. 2006-523850
  • PTL 2: Japanese Unexamined Patent Application Publication No. 2002-365657

SUMMARY OF INVENTION Technical Problem

In the FFS driving liquid crystal display apparatus, a fringe electric field is generated between an upper-layer slit electrode and a lower-layer planar electrode of a lower substrate during a rise time (a duration of time throughout which a display state changes from a dark state (black image displaying) to a light state (white image displaying)) and a vertical electric field is generated by a potential difference between the substrates during a fall time (a duration of time throughout which the display state changes from the light state (white image displaying)) to the dark state (black image displaying). The liquid crystal molecules are thus rotated by these electric fields, thereby achieving a fast response. On the other hand, as described in Patent Literature 1, only liquid crystal molecules in the vicinity of the slit electrodes are rotated when the fringe electric field is generated using the slit electrodes in the liquid crystal display apparatus having the liquid crystal molecules vertically aligned (see FIG. 66), and no sufficient transmittance results.

FIG. 64 is a schematic sectional view of a liquid crystal display panel having an electrode structure of a related art FFS driving method on a lower substrate. FIG. 66 illustrates simulation results of a director distribution, an electric field distribution, and a transmittance distribution of the liquid crystal display panel of FIG. 64. In a structure of the liquid crystal display panel of FIG. 64, a slit electrode is supplied with a constant voltage (for example, the constant voltage is 14 V. It is acceptable if a potential difference between the slit electrode and an opposite electrode 313 is a threshold value or above. The threshold value is intended to mean a voltage value that causes an electric field at which an optical change occurs in the liquid crystal layer, causing a change in a display state of the liquid crystal display apparatus.), and opposite electrodes 313 and 323 are respectively arranged on the substrate having the slit electrode and the opposite substrate. The opposite electrodes 313 and 323 are supplied with 7 V. FIG. 66 illustrates the simulation results during the rise time, more specifically, the voltage distribution, the distribution of directors D, the transmittance distribution (solid line).

PTL 2 discloses that the liquid crystal display apparatus having a three-layer structure performs comb driving to increase a response speed. However, PTL 2 describes only liquid crystal apparatuses of twisted nematic (TN) mode as a display mode in practice, and does not disclose anything about a liquid crystal apparatus of vertical alignment that provides advantageous features including the wide viewing angle and high-contrast characteristics. PTL 2 fails to describe an improvement in the transmittance and anything about a relationship between the electrode structure and the transmittance.

In view of the above problems, the present invention has been developed. It is an object of the present invention to provide a liquid crystal display panel and a liquid crystal display apparatus that achieve a sufficiently fast response, and a sufficient transmittance performance in the field of liquid crystal display panels and liquid crystal display apparatuses that contain liquid crystal molecules that are aligned in a direction vertical to a main substrate surface with no voltage applied to a liquid crystal layer.

Solution to Problem

The inventors of the present invention have studied vertically aligned liquid crystal display panels and vertically aligned liquid crystal display apparatuses that could satisfy both fast response and high transmittance requirements, and have focused studies on a three-layer electrode structure that is alignment-controlled by electric fields during both a rise period and a fall period. The inventors have studied further the electrode structure, and have found that a three-layer electrode structure appropriately performs switching between a vertical electric field application and an in-plane electric field application. The three-layer electrode structure includes a first substrate and a second substrate, each having electrodes, and a liquid crystal layer sandwiched between the first substrate and the second substrate. The electrodes of the second substrate are a pair of comb electrodes. The switching between the vertical electric field application and the in-plane electric field application is performed in response to an in-field electric field generated by a potential difference between the pair of comb electrode during the rise period and a vertical electric field generated by a potential difference between the substrates during the fall period. The inventors have found that the fast response is achieved by causing the electric fields to rotate the liquid crystal molecules during both the rise period and the fall period, and that the high transmittance is also achieved by the in-plane electric field in the comb driving. Having anticipated that it is possible to overcome the problem, the inventor have made the invention. A vertically aligned liquid crystal display apparatus having the three-layer electrode structure of the present invention provides fast response and high transmittance performances and in this point, the present invention is different from the related art disclosed in the related art literature. Furthermore, although the problem of response speed becomes outstanding at a low temperature environment, the present invention overcomes this problem as well, and further achieves sufficient transmittance.

The present invention relates to a liquid crystal display panel that includes a first substrate, a second substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. Each of the first substrate and the second substrate includes electrodes. The electrodes of the second substrate includes a pair of comb substrates and a planar electrode. The liquid crystal display panel is configured to align liquid crystal molecules in the liquid crystal layer in a direction horizontal to a substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate. The planar electrode is typically separated from the pair of comb electrode by an electrically resistive layer sandwiched therebetween. The electrically resistive layer is preferably an insulating layer. The insulating layer can be any insulator that is accepted as having an insulating property in the field of the present invention.

The pair of comb electrodes are preferably arranged to be opposed to each other in a plan view of a substrate main surface. The pair of comb electrodes appropriately generates the in-plane electric field between the comb electrodes. If a liquid crystal layer contains liquid crystal molecules having a positive dielectric anisotropy, the fast response performance and the high transmittance are achieved during the rise period. If the liquid crystal layer contains liquid crystal molecules having a negative dielectric anisotropy, the in-plane electric field rotates the liquid crystal molecules increasing the response speed during the fall period. It is sufficient if the electrodes of the first substrate and the second substrate cause a potential difference between the substrates. In this way, the vertical electric field is generated between the substrates during the fall period if the liquid crystal layer contains liquid crystal molecules having a positive dielectric anisotropy or during the rise period if the liquid crystal layer contains liquid crystal molecules having a negative dielectric anisotropy. The vertical electric field thus generated rotates the liquid crystal molecules, increasing the response speed.

FIG. 71 and FIG. 72 are schematic sectional views illustrating an embodiment of a comb electrode related to a liquid crystal display panel of the present invention. As illustrated in FIG. 71, a pair of comb electrodes 417 and 419 may be arranged on the same layer. The pair of comb electrodes 517 and 519 may also be arranged on different layers as illustrated in FIG. 72 as long as the effects of the present invention are provided, but the pair of comb electrodes is preferably arranged on the same layer. The pair of comb electrodes arranged on the same layer is intended to mean that each of the comb electrodes remains in contact with the common member (such as the insulating layer or the liquid crystal layer) on the side of the common member facing the liquid crystal layer and/or on the side of the common member opposite the liquid crystal layer.

The pair of comb electrodes preferably has comb tooth portions that run side by side in a plan view of the main surface of the substrate. The comb tooth portions of the pair of comb electrodes are preferably generally in parallel to each other. In other words, each of the electrodes of the pair has preferably a plurality of slits run generally in parallel to each other. FIG. 19 and other figures schematically illustrate a pair of comb electrodes having a single comb tooth portion. Typically, each comb electrode has two or more comb tooth portions.

The liquid crystal preferably contains liquid crystal molecules that are aligned to be vertical to the substrate main surface during a no-voltage application period. The phrase aligned to be vertical to the substrate main surface is intended to mean an alignment vertical to the substrate main surface that is accepted as vertically aligned to the substrate main surface in the technical field of the present invention, and includes a substantially vertical alignment. The liquid crystal preferably contains the liquid crystal molecules that are aligned to be vertical to the substrate main surface with an applied voltage less than a threshold value. The phrase “during the no-voltage application period” is intended to mean a substantial no-voltage application that is typically accepted as no voltage application in the technical field of the preset invention. Such vertical alignment liquid crystal is advantageous because of wide viewing angle and high-contrast characteristics, and has been finding more applications.

The electrodes of the pair of comb electrodes may be preferably different from each other in a potential range equal to or above a threshold voltage. For example, the threshold voltage is intended to mean a voltage value that gives rise to a transmittance of 5% with a transmittance in a light state being 100%. The phrase different from each other in the potential range equal to or above the threshold voltage is intended to mean that a driving operation with different potential levels is enabled at the threshold voltage or above, and in this way, the electric field applied to the liquid crystal is appropriately controlled. The upper limit of the preferably different potentials is 20 V, for example. In the arrangement of the different potentials, the one electrode of the pair is driven by a TFT, and the other electrode of the pair is driven by another TFT or is electrically connected to a lower layer electrode below the other electrode of the pair. The electrodes of the pair of comb electrode have thus different potentials. The width of a comb tooth portion of the pair of comb electrodes is preferably 2 μm or wider. The length between one comb tooth portion and a next comb tooth portion (referred to as a space in the description) is preferably from 2 μm to 7 μm, for example.

The liquid crystal display panel is preferably configured to align liquid crystal molecules in the liquid crystal layer in a direction vertical to a substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate. The electrode of the first substrate is preferably a planar electrode. In this description, the planar electrode includes a set of electrically connected electrodes in a plurality of pixels. For example, the planar electrode includes a set of electrically connected electrodes in all the pixels, and a set of electrically connected electrodes along a pixel line. The second substrate preferably further includes a planar electrode. With this arrangement, the vertical electric field is appropriately applied to achieve fast response. In particular, the arrangement with the electrode on the first substrate being a planar electrode and the electrode on the second substrate also being a planar electrode appropriately generates the vertical electric field in response to the potential difference between the substrates during the fall period. The fast response is thus achieved. In order to generate the in-plane electric field and the vertical electric field in a preferred fashion, electrodes on the side of the second substrate facing the liquid crystal layer (upper layer electrodes) are preferably set to be the pair of comb electrodes, and an electrode on side of the second substrate opposite the liquid crystal layer (lower layer substrate) is preferably set to be a planar electrode. For example, the planar electrode on the second substrate is separated by an insulating layer that is beneath the pair of comb electrodes (on the side of the second substrate opposite the liquid crystal layer). The planar electrodes on the second substrate are preferably electrically connected along a pixel line. Alternatively, each planar electrode may also be formed on a per pixel basis. The comb electrodes may be electrically connected to the planar electrode below the comb electrode. If the planar electrodes are electrically connected along a pixel line in this case, the comb electrodes are also electrically connected along the pixel line, and this arrangement is also one of the preferred embodiments of the present invention. The planar electrode of the second substrate is preferably at least planar where a portion of the planar electrode overlaps the electrode of the first substrate in a plan view of the substrate main surface. The phrase electrically connected along the pixel line is intended to mean that electrodes in a plurality of pixels are electrically connected along at least one of a column and a row of the pixels. The electrodes do not have to be electrically connected along all the pixel lines. It is sufficient if electrodes are electrically substantially connected along a pixel line in the liquid crystal display panel.

The planar electrodes are preferably electrically connected along the same pixel column. The same pixel column is a column of pixels that are arranged along a gate bus line in an active matrix substrate in a plan view of the substrate main surface if the second substrate is an active matrix substrate. If the planar electrodes on the first substrate and/or the planar electrodes on the second substrate are electrically connected along the same pixel column in this way, voltage can be applied to the electrodes so that a potential difference takes place on of the pixels of an even-numbered bus line or on the pixels of an odd-numbered bus line. The vertical electric field is thus generated to achieve fast response.

The planar electrode on the first substrate and/or the planar electrode on the second substrate are intended to mean any planar shape that is accepted as planar in the technical field of the present invention. The planar electrode may partially have an orientation anchoring structure such as a rib or a slit, or may have an orientation anchoring structure in the center of each pixel in a plan view, but preferably, the planar electrode has no orientation anchoring structure.

The liquid crystal layer is aligned in directions including a horizontal direction with respect to the substrate main surface with a threshold voltage or higher in response to an electric field generated between the pair of comb electrodes or an electric filed generated between the first substrate and the second substrate. Particularly, the liquid crystal layer preferably contains liquid crystal molecules that are aligned in a horizontal direction in particular. The phrase aligned in the horizontal direction is intended to mean an alignment that is accepted as aligned in the horizontal direction in the technical field of the present invention. Transmittance is thus increased. Preferably, the liquid crystal molecules contained in the liquid crystal layer substantially include liquid crystal molecules that align in the horizontal direction with respect to the substrate main surface with the threshold voltage or above.

The liquid crystal preferably contains the liquid crystal molecules having a positive dielectric anisotropy (the positive-type liquid crystal layer). The liquid crystal molecules having a positive dielectric anisotropy are aligned in a certain direction with an electric field applied. Alignment control of the liquid crystal is easy, and the liquid crystal has the fast response feature. The liquid crystal also preferably contains the liquid crystal molecules having a negative dielectric anisotropy (negative-type liquid crystal molecules). In this way, transmittance is increased. From the standpoint of the fast response, the liquid crystal molecules are preferably liquid crystal molecules having a positive dielectric anisotropy, and from the standpoint of the transmittance, the liquid crystal molecules are preferably liquid crystal molecules having a negative dielectric anisotropy.

At least one of the first substrate and the second substrate includes an alignment layer on the side thereof facing the liquid crystal layer. The alignment layer is preferably a vertical alignment layer. The alignment layers include an alignment layer manufactured of an organic material or an inorganic material, and an alignment layer manufactured of an optically active material, among other alignment layers. An alignment layer that has not undergone an alignment process such as a rubbing process is also acceptable. Using an alignment layer, such as an alignment layer manufactured of an organic material or an inorganic material, or an optical alignment layer, which needs no alignment process, the process of the liquid crystal display panel is facilitated, and costs in the process are reduced. The reliability and yield of the liquid crystal display panel are increased. If the rubbing process is performed, an impure substance such as a rubbing cloth may be included. The inclusion of the impure substance leads to pollution of the liquid crystal, or a point defect is caused by a foreign substance, or non-uniform rubbing on the liquid crystal display panel causes a display uneveness. The liquid crystal display panel is free from these problems. At least one of the first substrate and the second substrate preferably includes a polarizer on the side thereof opposite the liquid crystal layer. The polarizer is preferably a circularly polarizing plate. This arrangement further promotes a transmittance increasing effect. The polarizer is also preferably a linearly polarizing plate. This arrangement improves viewing angle characteristics.

In the liquid crystal display panel of the present invention, a potential difference is caused at least between the electrode of the first substrate and the electrode of the second substrate (such as a planar electrode) to generate a vertical electric field. In a preferred embodiment, the potential difference caused between the electrode of the first substrate and the electrode of the second substrate is preferably higher than a potential difference caused between the electrodes of the second substrate (for example, between the pair of comb electrodes). For example, the potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 7.5 V and 0 V, respectively, and the potentials of the pair of comb electrodes on the second electrode are set to be 0 V. The potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 7.5 V and 15 V, respectively, and the potentials of the pair of comb electrodes on the second substrate are set to be 15 V. The potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 0 V and 15 V, respectively, and the potentials of the pair of comb electrodes on the second substrate are set to be 15 V.

Subsequent to the generation of the vertical electric field, preferably, an operation to cause substantially no potential difference between the planar electrode of the first substrate and the planar electrode of the second substrate and to cause substantially no potential difference between the pair of comb electrodes on the second substrate is preferably performed (called an initialization process step in the description). In other words, a driving operation is preferably performed to cause substantially no potential difference between all the electrodes including the electrode of the first substrate (such as the planar electrode) and the electrodes on the second substrate (such as the pair of comb electrodes and the planar electrode). With this arrangement, the alignment of the liquid crystal in the vicinity of an edge of the planar electrode in particular is appropriately controlled, and the transmittance is increased. In this way, the transmittance which remains raised unless the electrodes are set to be equipotential is sufficiently decreased to an initial black state (as denoted by an area enclosed by a broken line in FIG. 8, for example). The initialization process step is simply a driving operation that causes no potential difference between all the electrodes in practice. In one example, at least one electrode of a comb electrode pair may be kept floating with a TFT in an off state. In another example, a constant voltage is applied to at least one electrode of the comb electrode pair with all the TFTs in an on state. In yet another example, the TFTs connected to even-numbered lines or odd-numbered lines are set to be in the on state, and a constant voltage is applied to one electrode of the comb electrode pair on a per even-numbered line basis or on a per odd-numbered line basis. The initialization process step is preferably performed subsequent to the generation of the vertical electric field. Another electric field may be generated subsequent to the generation of the vertical electric field, but the initialization process step is preferably performed immediately subsequent to the generation of the vertical electric field.

In the liquid crystal display panel of the present invention, a potential difference is caused at least between the electrodes on the second substrate (such as the pair of comb substrates) to generate an in-plane electric field. The potential difference caused between the electrodes of the second substrate is preferably higher than a potential difference caused between the electrode on the first substrate and the electrode on the second substrate (for example, between the planar electrodes). For example, the potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 7.5 V and 0 V, respectively, and the potentials of the pair of comb electrodes on the second electrode are set to be 15 V and 0 V, respectively. The potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 7.5 V and 7.5 V, respectively, and the potentials of the pair of comb electrodes on the second substrate are set to be 15 V and 0 V, respectively. The potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 0 V and 0 V, respectively, and the potentials of the pair of comb electrodes on the second substrate are set to be 15 V and 0 V, respectively. The potential difference caused between the electrodes of the second substrate may be set to be lower than a potential difference caused between the electrode on the first substrate and the electrode on the second substrate. In order to perform low gradation tone display using the in-plane electric field between the comb electrodes, the potential of the planar electrode on the first substrate and the potential of the planar electrode on the second substrate are set to be 7.5 V and 0 V, respectively, and the potentials of the pair of comb electrodes on the second substrate are set to be 10 V and 5 V (a potential difference of 5 V between comb tooth portions), respectively.

A potential change is inverted by applying a voltage to lower layer electrodes (the planar electrodes on the second substrate) commonly connected on a per even-numbered line basis and on a per odd-numbered line basis. The potential of the electrodes biased at a constant voltage may be an intermediate potential. If the potential of the electrodes biased at a constant voltage is considered to be 0 V, it is interpreted that the voltage to be applied to the lower-layer electrodes is inverted in polarity on a per bus line basis.

The first substrate and the second substrate of the liquid crystal display panel of the present invention are a pair of substrates to hold a liquid crystal therebetween, and include as a base an insulating substrate of glass, resin, or the like, and the liquid crystal display panel is produced by arranging wirings, electrodes, and color filters on the insulating substrate.

Preferably, at least one electrode of the pair of comb electrodes is a pixel electrode, and the substrate having the pair of comb electrodes is an active matrix substrate. The liquid crystal display panel of the present invention is applicable to any of transmissive, reflective, and semi-transmissive liquid crystal display apparatuses.

The present invention also relates to a liquid crystal display apparatus that includes the liquid crystal display panel of the present invention. A preferred embodiment of the liquid crystal display panel in the liquid crystal apparatus of the present invention is identical to a preferred embodiment of the liquid crystal display panel of the present invention described above. The liquid crystal display apparatuses include a display of each of a personal computer, a television, on-board apparatuses including a car navigation system, and a mobile information terminal such as a cell phone. The liquid crystal display apparatus is preferably applied to the on-board apparatuses, including the car navigation system, which may be used in a low-temperature environment.

The present invention also relates to a thin-film transistor array substrate having thin-film transistors. Electrodes of the thin-film transistor array include a pair of comb electrodes, and a planar electrode, and at least each one electrode selected from a group including the pair of comb electrodes and the planar electrode is electrically connected along a pixel line.

The planar electrodes are preferably electrically connected along the pixel line. More preferably, the planar electrode includes a transparent conductor and a metal conductor connected to the transparent conductor. In this way, the electrode is rendered low-resistive, preventing waveform from being distorted. The resistance of each electrode is substantially high in a large-scale panel. The use of such electrode in a large-scale liquid crystal apparatus is particularly useful in view of the effectiveness of the low-resistance electrode.

One-side electrodes of the pairs of comb electrodes are preferably electrically connected to each other along a pixel line. More preferably, at least the one-side electrodes are manufactured of a transparent conductor and a metal conductor electrically connected to the transparent conductor. For the same reason described above, such a liquid crystal driving apparatus is preferably applied to a large-scale liquid crystal display apparatus. At least one-side electrodes of the pairs of comb electrodes are preferably electrically connected to the planar electrode.

The phrase the electrodes electrically connected along the pixel line is intended to mean that the electrodes are electrically connected together at least along the same pixel line. For example, the electrodes may be connected together on a per pixel line basis, or the electrodes may be connected together every n lines of the pixel lines, and either method is preferable. Here, n is an integer equal to 2 or above. The phrase the electrodes electrically connected every plural number of lines (n lines) is intended to mean that the electrodes corresponding to every plural lines of the pixel lines are electrically connected together. For example, the electrodes may be electrically connected together on every odd-numbered line or on every even-numbered line. If the electrodes are connected every plural number of lines, the connected line is concurrently inverted in potential.

The present invention also relates to a thin-film transistor array substrate having thin-film transistors. Electrodes of the thin-film transistor array include a pair of comb electrodes, and a planar electrode. At least one-side electrode of the pair of comb electrodes is electrically connected to the planar electrode.

The present invention also relates to a liquid crystal display apparatus that includes the thin-film transistor array. A preferred embodiment of the thin-film transistor array in the liquid crystal apparatus of the present invention is identical to a preferred embodiment of the thin-film transistor array of the present invention described above. The liquid crystal display apparatus finds the applications described above.

The configuration of the liquid crystal display panel and the liquid crystal display apparatus of the present invention includes the elements described above as necessary components, and the use of other components in the configuration is optional. Other configuration of ordinary liquid crystal display panels and liquid crystal display apparatuses may also be applied.

The embodiments described above may be appropriately combined within the scope of the present invention.

Advantageous Effects of Invention

In accordance with the liquid crystal display panel and the liquid crystal display apparatus of the present invention, each of a first substrate and a second substrate includes electrodes, and the second substrate includes a pair of comb electrodes and a planar electrode. The liquid crystal display panel and the liquid crystal display apparatus achieve a sufficiently fast response and a sufficient transmittance performance.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic sectional view of a liquid crystal display panel of a first embodiment during the generation of an in-plane electric field.

FIG. 2 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of a vertical electric field.

FIG. 3 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of the in-plane electric field.

FIG. 4 illustrates simulation results of the liquid crystal display panel of FIG. 3.

FIG. 5 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of the vertical electric field.

FIG. 6 illustrates simulation results of the liquid crystal display panel of FIG. 5.

FIG. 7 is a graph illustrating a comparison of response waveforms through simulation of comb driving and FFS driving.

FIG. 8 is a graph illustrating a measurement value of a drive response waveform and a rectangular waveform applied to each electrode in the first embodiment.

FIG. 9 is a graph illustrating a relationship between a maximum transmittance and a cell thickness d in the first embodiment.

FIG. 10 is a graph illustrating a relationship between a maximum transmittance and a space S in the first embodiment.

FIG. 11 is a schematic sectional view illustrating a liquid crystal display panel of a second embodiment during the generation of an in-plane electric field.

FIG. 12 is a schematic sectional view illustrating the liquid crystal display panel of the second embodiment during the generation of a vertical electric field.

FIG. 13 is a graph illustrating a rectangular waveform applied to each electrode (driving waveform) in the second embodiment.

FIG. 14 is a schematic sectional view illustrating a liquid crystal display panel of a third embodiment during the generation of an in-plane electric field.

FIG. 15 is a schematic sectional view illustrating the liquid crystal display panel of the third embodiment during the generation of a vertical electric field.

FIG. 16 is a graph illustrating a rectangular waveform applied to each electrode (driving waveform) in the third embodiment.

FIG. 17 is a graph illustrating measurement values of drive response waveforms in accordance with the first through third embodiments.

FIG. 18 is a schematic sectional view of the liquid crystal display panel of a first embodiment.

FIG. 19 is a plan view of a picture element in the liquid crystal display panel of the first embodiment.

FIG. 20 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the first embodiment.

FIG. 21 illustrates a potential change of each electrode in the liquid crystal display panel of the first embodiment.

FIG. 22 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the first embodiment during the generation of an in-plane electric field.

FIG. 23 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the first embodiment during the generation of a vertical electric field.

FIG. 24 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the first embodiment during a initialization process step subsequent to the generation of the vertical electric field.

FIG. 25 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the first embodiment during the generation of the in-plane electric field.

FIG. 26 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the first embodiment during the generation of the vertical electric field.

FIG. 27 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the first embodiment during the initialization process step subsequent to the generation of the vertical electric field.

FIG. 28 is a schematic sectional view of the liquid crystal display panel of a second embodiment.

FIG. 29 is a plan view of a picture element in the liquid crystal display panel of the second embodiment.

FIG. 30 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the second embodiment.

FIG. 31 illustrates a potential change of each electrode in the liquid crystal display panel of the second embodiment.

FIG. 32 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the second embodiment during the generation of an in-plane electric field.

FIG. 33 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during an initialization process step subsequent to the generation of the in-plane electric field.

FIG. 34 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during the generation of a vertical electric field.

FIG. 35 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during a initialization process step subsequent to the generation of the vertical electric field.

FIG. 36 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the second embodiment during the generation of the in-plane electric field.

FIG. 37 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the initialization process step subsequent to the generation of the in-plane electric field.

FIG. 38 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the generation of the vertical electric field.

FIG. 39 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the initialization process step subsequent to the generation of the vertical electric field.

FIG. 40 is a schematic sectional view of the liquid crystal display panel of a modification of the second embodiment.

FIG. 41 is a plan view of a picture element in the liquid crystal display panel of the modification of the second embodiment.

FIG. 42 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the modification of the second embodiment.

FIG. 43 illustrates a potential change of each electrode in the liquid crystal display panel of the modification of the second embodiment.

FIG. 44 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of an in-plane electric field.

FIG. 45 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of a vertical electric field.

FIG. 46 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the modification of the second embodiment during an initialization process step subsequent to the generation of the vertical electric field.

FIG. 47 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of the in-plane electric field.

FIG. 48 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of the vertical electric field.

FIG. 49 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during an initialization process step subsequent to the generation of the vertical electric field.

FIG. 50 is a schematic sectional view of the liquid crystal display panel of a third embodiment.

FIG. 51 is a plan view of a picture element in the liquid crystal display panel of the third embodiment.

FIG. 52 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the third embodiment.

FIG. 53 illustrates a potential change of each electrode in the liquid crystal display panel of the third embodiment.

FIG. 54 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the third embodiment during the generation of an in-plane electric field.

FIG. 55 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the third embodiment during the generation of a vertical electric field.

FIG. 56 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the third embodiment during an initialization process step subsequent to the generation of the vertical electric field.

FIG. 57 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the third embodiment during the generation of the in-plane electric field.

FIG. 58 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the third embodiment during the generation of the vertical electric field.

FIG. 59 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the third embodiment during the initialization process step subsequent to the generation of the vertical electric field.

FIG. 60 is a schematic plan view illustrating a driving operation of the present invention.

FIG. 61 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention.

FIG. 62 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention.

FIG. 63 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention.

FIG. 64 is a schematic sectional view illustrating a liquid crystal display panel of a first comparative example during the generation of a fringe electric field.

FIG. 65 is a schematic plan view illustrating the liquid crystal display panel of FIG. 64.

FIG. 66 illustrates simulation results of the liquid crystal display panel of FIG. 64.

FIG. 67 is a graph illustrating a response waveform obtained through simulation of comb driving in a TN mode of a second comparative example.

FIG. 68 illustrates simulation results of the liquid crystal display panel of the second comparative example.

FIG. 69 illustrates simulation results of the liquid crystal display panel of the second comparative example.

FIG. 70 illustrates simulation results of the liquid crystal display panel of the second comparative example.

FIG. 71 is a schematic sectional view of an example of a comb electrode of the liquid crystal display panel of the present invention.

FIG. 72 is a schematic sectional view of an example of the comb electrode of the liquid crystal display panel of the present invention.

FIG. 73 is a schematic plan view illustrating an example of a thin-film transistor used for a pixel electrode of the liquid crystal display panel of the present invention.

 DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention are described further in detail below. The present invention is not limited to these embodiments. In the description, the term pixel refers a picture element (subpixel) unless otherwise noted. The term subframe is opposed to the term frame during which all the pixels (including RGB pixels) are used to display an image, and refers to time to display one color when continuous displaying of each color is performed in one frame using all or part of picture elements through field sequential (time-division) driving. In the description, the term subframe refers to a period for displaying one color. A planar electrode may partially have an orientation anchoring structure such as a rib and/or a slit as long as the planar electrode is accepted as planar in the technical field of the present invention. In principle, however, the planar electrode preferably has no orientation anchoring structure. Of a pair of substrates having a liquid crystal layer interposed therebetween, a substrate on a display screen side is referred to as an upper substrate and a substrate opposite the display screen side is referred to as a lower substrate. Of electrodes arranged on the substrates, an electrode on the side of the display screen is referred to as an upper layer electrode, and an electrode on the side opposite the display screen is referred to as a lower layer electrode. Furthermore, a circuit substrate of an embodiment (a second substrate) is referred to as a thin-film transistor (TFT) substrate or a array substrate because the circuit substrate has TFTs. In the present embodiment, both during a rise time (an in-plane electric field applied) and during a fall time (a vertical electric file applied), the TFT is turned on so that a voltage is applied to at least one electrode of a pair of comb electrodes (pixel electrode).

In the discussion of each embodiment, members or portions having the same function are identified with the same symbol. In drawings, unless otherwise noted, a label (i) indicates the potential of one electrode of the comb electrodes on the topside of the lower substrate, a label (ii) indicates the potential of the other electrode of the comb electrodes on the topside of the lower substrate, a label (iii) indicates the potential of a planar electrode on the underside of the lower substrate, and a label (iv) indicates the potential of a planar electrode of the upper substrate.

First Embodiment

FIG. 1 is a schematic sectional view of a liquid crystal display panel of a first embodiment during the generation of an in-plane electric field. FIG. 2 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of a vertical electric field. As illustrated in FIG. 1 and FIG. 2, a broken line indicates the direction of a generated electric field. The liquid crystal display panel of the first embodiment has a vertically aligned three-layer electrode structure including liquid crystal molecules 31 as a positive-type liquid crystal (an upper layer electrode on the lower substrate as a second layer is a comb electrode). During the rise time, the in-plane electric field generated by a potential difference of 14 V between a pair of comb electrodes 16 (a comb electrode 17 having a potential of 0 V and a comb electrode 19 having a potential of 14 V) causes the liquid crystal molecules to rotate as illustrated in FIG. 1. Then, there occurs substantially no potential difference between the substrates (the opposite electrode 13 having a potential of 7 V and the opposite electrode 23 having a potential of 7 V).

During the fall time, the vertical electric field generated by a potential difference of 7 V between the substrates (between the opposite electrode 13, the comb electrode 17 and the comb electrode 19, each having a potential of 14 V, and the opposite electrode 23 having a potential of 7 V) causes the liquid crystal molecules to rotate as illustrated in FIG. 2. Then, there occurs substantially no potential difference between the pair of the comb electrodes 16 (including the comb electrode 17 having a potential of 14 V and the comb electrode 19 having a potential of 14 V).

During both the rise time and the fall time, the electric fields rotate the liquid crystal molecules, thereby achieving a high response. More specifically, during the rise time, the in-plane electric field between a pair of comb electrodes sets the liquid crystal molecules in an on state, thereby providing a high transmittance. During the fall time, the vertical electric field between the substrates sets the liquid crystal molecules in an on state, thereby achieving the fast response. Furthermore, the in-plane electric field of comb driving also increases transmittance. Note that the positive-type liquid crystal is employed as a liquid crystal in the first embodiment and subsequent embodiments, but a negative-type liquid crystal may be used instead of the positive-type liquid crystal. If the negative-type liquid crystal is used, a potential difference between the substrates horizontally aligns the liquid crystal molecules, and a potential difference between a pair of comb electrodes vertically aligns the liquid crystal molecules. The transmittance performance becomes satisfactory in this way, and the fast response is achieved by rotating the liquid crystal molecules by the electric fields during the rise time and the fall time. In the same manner as with the positive-type liquid crystal, the transmittance during the black image display is sufficiently reduced by aligning the liquid crystal molecules sufficiently in a vertical direction in the initialization process step. Preferably performed in this case are a driving operation to cause a potential difference at least between the opposite electrodes respectively arranged on the upper substrate and the lower substrate, a driving operation to cause a potential difference at least between the pair of comb electrodes, and a driving operation to cause no potential difference between the opposite electrodes and between the pair of comb electrodes in that order. In the description, labels (i) and (ii) indicate the potentials of the pair of comb electrodes, a label (iii) indicates the potential of the planar electrode on the lower layer substrate, and a label (iv) indicates the potential of the planar electrode of the upper layer substrate.

As illustrated in FIG. 1 and FIG. 2, the liquid crystal display panel of the first embodiment includes an array substrate 10, a liquid crystal layer 30 and an opposite substrate 20 (a color filter substrate) laminated in that order from the back side of the liquid crystal display panel to the viewing screen side thereof. The liquid crystal display panel of the first embodiment vertically aligns the liquid crystal molecules when the potential difference between the comb electrodes is lower than a threshold voltage as illustrated in FIG. 2. As illustrated in FIG. 1, when the voltage difference between the comb electrodes is equal to or above the threshold voltage, the electric field generated between the comb electrodes 17 and 19 (the pair of the comb electrodes 16) as upper layer electrodes formed on a glass substrate 11 (the second substrate) tilts the liquid crystal molecules between the comb electrodes at a horizontal direction. The transmittance is thus controlled. An insulating layer 15 is sandwiched between the planar lower layer electrode 13 (the opposite electrode 13) and the comb electrodes 17 and 19 (the pair of the comb electrodes 16). The insulating layer 15 may be manufactured of an oxide film SiO2, a nitride film SiN, an acrylic resin, or a combination thereof.

A polarizer, though not illustrated in FIG. 1 and FIG. 2, is arranged on the sides of the two substrates opposite the liquid crystal layer. The polarizers may include a circularly polarizing plate and a linearly polarizing plate. An alignment layer is arranged on the side of each of the two substrates facing the liquid crystal layer. An organic alignment layer or an inorganic alignment layer may be acceptable as the alignment layer as long as the alignment layer vertically aligns the liquid crystal molecules with respect to the layer surface.

A voltage supplied via a video signal line is applied to the comb electrode 19 driving the liquid crystal via a thin-film transistor (TFT) at a timing when a scanning signal line is selected. In the present embodiment, the comb electrode 17 and the comb electrode 19 are formed at the same layer. Forming the comb electrode 17 and the comb electrode 19 at the same layer is preferable. Forming the comb electrode 17 and the comb electrode 19 at different layers may also be acceptable as long as the effects of the present invention, more specifically, the increase in the transmittance by applying the in-plane electric field in response to the potential difference between the comb electrodes, is achieved. The comb electrode 19 is connected to a drain electrode that extends from the TFT via a contact hole. Note that the opposite electrodes 13 and 23 are planar in FIG. 1 and FIG. 2 and that the opposite electrodes 13 are commonly connected on each of the even-numbered line and the odd-numbered line of the gate bus lines. These electrodes are also referred to as a planar electrode in the description. The opposite electrodes 23 corresponding to all pixels are commonly connected.

An electrode width of the comb electrodes L is 2.4 μm in the present embodiment and, preferably, is 2 μm or wider, for example. An electrode spacing S between the comb electrodes is 2.6 μm in the present embodiment, and, preferably, is 2 μm or wider, for example. Note that an upper limit of the electrode spacing is preferably 7 μm. A ratio of the electrode width L to the electrode spacing (L/S) is preferably 0.4 through 3, for example. More preferably, the lower limit of the ratio is 0.5, and the upper limit of the ratio is 1.5.

A cell gap d is 5.4 μm here, and is preferably within a range of from 2 μm to 7 μm. In the description, the cell gap D (a thickness of the liquid crystal layer) is preferably calculated by averaging the thickness of the whole area of the liquid crystal layer in the liquid crystal display panel.

Verification of Response Performance and Transmittance Through Simulation

FIG. 3 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of the in-plane electric field. In the driving operation of the comb driving of the first embodiment, the in-plane electric field, generated between the pair of the comb electrodes 16 (including the comb electrode 17 having a potential of 0 V and the comb electrode 19 having a potential of 14 V), can rotate the liquid crystal molecules in a wide region between the pair of comb electrodes (see FIG. 3 and FIG. 4).

FIG. 4 illustrates simulation results of the liquid crystal display panel of FIG. 3. FIG. 4 illustrates the simulation results, at 2.2 ms after a rise time, of directors D, electric fields, and transmittance distribution (as illustrated in drawings (graphs) below, no driving is performed during a first 0.4 ms duration). A solid-line plot represents transmittance. The director D represents an alignment direction of the long axis of the liquid crystal molecule. In the simulation conditions, the cell thickness was 5.4 μm, and the comb tooth spacing was 2.6 μm.

If the in-plane electric field of the comb driving is applied in the liquid crystal display panel of the first embodiment, the liquid crystal molecules are rotated in a wide region between the comb electrodes, and a high transmittance was achieved (the transmittance was 18.6% (see FIG. 7) in simulation results, and the actual measurement transmittance was 17.7% (see FIG. 8 and other drawings)). On the other hand, no sufficient transmittance resulted in a first comparative example to be discussed below (the FFS driving in the related art literature). Note that FIG. 5 is a schematic sectional view of the liquid crystal display panel of the first embodiment during the generation of the vertical electric field. The vertical electric field generated by a potential difference of 7 V between the substrates (the opposite electrode 13, the comb electrode 17, and the comb electrode 19, each having a potential of 14 V and the opposite electrode 23 having a potential of 7 V) rotates the liquid crystal molecules. FIG. 6 illustrates simulation results of the liquid crystal display panel of FIG. 5. FIG. 6 illustrates the simulation results, at 3.5 ms time point after the end point of the fall time (at a time point of 2.8 ms), of directors D, electric fields, and transmittance distribution.

FIG. 7 is a graph illustrating a comparison of response waveforms through simulation of comb driving and FFS driving. Since no driving is performed for an initial duration of 0.4 ms, a rise period (an in-plane electric field application period) is 2.4 ms, and a fall period (a vertical electrical field application period) is 0.8 ms. The comb driving (the first embodiment) is now compared with the FFS driving (the first comparative example) to be discussed below. In the simulation condition, the cell thickness was 5.4 μm, and the electrode spacing of the pair of comb electrodes was 2.6 μm.

A response speed is analyzed as below. The transmittance (18.6%) obtained through the comb driving of the first embodiment is higher than the transmittance (3.6%) obtained through the FFS driving of the first comparative example. If a target of a transmittance of 3.6% is set in the comb driving of the first embodiment, a faster response than the FFS driving is achieved using overdrive technique. More specifically, the liquid crystal is set to respond faster by applying a voltage higher than a rated voltage needed to achieve a transmittance of 3.6% through the comb driving. The voltage applied is decreased to the rated voltage at the timing when the target transmittance is achieved. The response time at the rise is thus shortened. As illustrated in FIG. 7, for example, the applied voltage is lowered to the rated voltage at a 0.6 ms time point 41, thereby shortening the response time at the rise. The response time at the fall from the same transmittance remains the same as at the rise.

Verification of Response Performance and Transmittance Through Actual Measurements

FIG. 8 is a graph illustrating a measurement value of a drive response waveform and a rectangular waveform applied to each electrode in the first embodiment. In the same manner as the above-described simulation, an evaluation cell had a cell thickness of 5.4 μm, and an electrode spacing of 2.6 μm between the pair of comb electrodes. The measured temperature was 25° C.

The voltages were applied to the electrodes at the rise and fall as illustrated in FIG. 3 and FIG. 5 so that the in-plane electric field and the vertical electric field were respectively applied to the liquid crystal molecules. More specifically, the rise period corresponded to a comb driving of 2.4 ms (the first embodiment) between the pair of comb electrodes, and the fall period corresponded to a vertical electric field driving of 0.8 ms between the pair of comb electrodes and the lower layer electrode on the lower substrate, and the upper layer electrode on the upper substrate (the pair of comb electrode 17 and comb electrode 19 and the opposite electrode 13, and the opposite electrode 23) (see FIG. 8 for an application voltage waveform of each electrode).

The actual measurement results were a maximum transmittance of 17.7% (opposed to a transmittance of 18.6% in simulation) which was higher than in the first comparative example to be discussed below (a transmittance of 3.6% in simulation). A transmittance of 10%-90% (with the maximum transmittance set to 100%) and a response speed of 0.9 ms were obtained at the rise, and a transmittance of 90%-10% (with the maximum transmittance set to 100%) and a response speed of 0.4 ms were obtained at the fall. A high speed performance was thus achieved at both the rise and fall.

The inventors have studied preferred comb tooth electrode width (L (Line)), comb electrode spacing (S (Space)), and cell width (d) for the vertical electric field application and the in-plane electric field application.

Relationship Between Transmittance and Line Width (L)

The transmittance increases in proportion to a decrease of the comb tooth electrode width L. However, if the comb tooth electrode width L is set to be too narrow, problems related to device manufacturing, such as leakage and open connection, arise. The comb tooth electrode width L is preferably 2 μm or wider.

Relationship of Transmittance with Cell Thickness d and Comb Tooth Electrode Spacing S

FIG. 9 is a graph illustrating a relationship between a maximum transmittance and a cell thickness d in the first embodiment. FIG. 10 is a graph illustrating a relationship between a maximum transmittance and a space S in the first embodiment. The response speed becomes lower as the cell thickness d and the spacing S increase more. From the standpoint of the response speed, the smaller the cell thickness d and the spacing S are, the better the response speed is. However, if the cell thickness d and the spacing S are too small, there is a possibility that problems related to device manufacturing, such as leakage and open connection, arise. For this reason, the cell thickness d and the spacing S are desirably 2 μm or larger. Next, the maximum transmittance was simulated with the cell thickness d and the spacing D varied using LCD MASTER (see FIG. 9, FIG. 10, Table 1 and Table 2). The maximum transmittance increased as both the cell thickness d and the spacing S increased from 2 μm. When the cell thickness d and the spacing S exceeded 7 μm, the maximum transmittance began to greatly decrease. For this reason, the cell thickness d and the spacing S are desirably 7 μm or smaller. Therefore, both the cell thickness d and the spacing S are desirably 2 μm or larger and 7 μm or smaller.

TABLE 1 Cell thickness (μm) Maximum transmittance 2 6.6% 3 14.5% 4 20.4% 5 22.8% 6 23.0% 7 22.6% 10 19.1% 15 19.2%

TABLE 2 Space (μm) Maximum transmittance 2 19.2% 3 20.0% 4 21.4% 5 22.4% 6 23.0% 7 23.3% 8 22.7% 9 22.5%

Second Embodiment

FIG. 11 is a schematic sectional view illustrating a liquid crystal display panel of a second embodiment during the generation of an in-plane electric field. FIG. 12 is a schematic sectional view illustrating the liquid crystal display panel of the second embodiment during the generation of a vertical electric field. FIG. 13 is a graph illustrating a rectangular waveform applied to each electrode (driving waveform) in the second embodiment.

In the driving method described with reference to the first embodiment, the opposite electrode 13 and the opposite electrode 23 are supplied with an intermediate voltage (7 V) of a potential difference (14 V) between the pair of comb electrodes. In the second embodiment, the opposite electrode 113 is set to be equipotential with the comb electrode 117 as one electrode of the pair of comb electrodes, and the opposite electrode 123 is set to be at an intermediate potential (7 V) of the potential difference (14 V) of the pair of comb electrodes (the second embodiment). The rest of the second embodiment remains unchanged from the first embodiment.

Third Embodiment

FIG. 14 is a schematic sectional view illustrating a liquid crystal display panel of a third embodiment during the generation of an in-plane electric field. FIG. 15 is a schematic sectional view illustrating the liquid crystal display panel of the third embodiment during the generation of a vertical electric field. FIG. 16 is a graph illustrating a rectangular waveform applied to each electrode (driving waveform) in the third embodiment.

In the third embodiment, an opposite electrode 213 is set to be equipotential with a comb electrode 217 and an opposite electrode 223 is set to 0 V. The rest of the third embodiment remains unchanged from the first embodiment.

FIG. 17 is a graph illustrating measurement values of drive response waveforms in accordance with the first through third embodiments. In the second and third embodiments featuring different driving methods, the response performance and the transmittance as good as in the first embodiment were measured. For example, an evaluation cell had a cell thickness of 5.4 μm, and an electrode spacing of 2.6 μm between the pair of comb electrodes. The measured temperature was 25° C. As the first embodiment, it was verified that as the first embodiment the second and third embodiments also achieved response and transmittance performances higher than those of the first comparative example (with a simulation transmittance of 3.6%) as illustrated in FIG. 17 while maintaining high response performance.

TFT Driving Method First Embodiment

FIG. 18 is a schematic sectional view of the liquid crystal display panel of a first embodiment. FIG. 19 is a plan view of a picture element in the liquid crystal display panel of the first embodiment. FIG. 20 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the first embodiment. FIG. 21 illustrates a potential change of each electrode in the liquid crystal display panel of the first embodiment. In the driving method of each module of the first embodiment, two TFTs are driven on a per picture element basis. As illustrated in FIG. 18 through FIG. 21, a chain line with two dots denotes a wiring electrically connected to a lower layer electrode on the lower substrate. A chain line with one dot denotes a wiring electrically connected to one comb electrode of the pair of comb electrodes on the lower substrate. A dotted line with narrower intervals denotes a wiring electrically connected to the other comb electrode of the pair of comb electrodes. A broken line with wider intervals denotes a wiring electrically connected to the electrode on the upper substrate. Each of the lower layer electrodes also serves as a Cs electrode, and the lower layer electrodes are commonly connected on a per even-numbered line basis and on a per odd-numbered line basis. As illustrated in FIG. 18, Cs denotes a storage capacitor formed of overlapping portions of the comb electrode and the Cs electrode, Clc1 denotes a liquid crystal capacitor formed between the pair of comb electrodes, and Clc2 denotes a liquid crystal capacitor formed between the electrodes of the pair of substrates.

In a picture element at an N-th row, a voltage applied to the lower layer electrode is 7.5 V during light image displaying, then changes to 15 V during dark displaying (black image displaying), and becomes 7.5 V in the initialization process step. In a picture element at an (N+1)-th row, a voltage applied to the lower layer electrode is 7.5 V during the light image displaying, then changes to 0 V during the dark displaying (black image displaying), and then becomes 7.5 V in the initialization process step. The N-th row may be an even-numbered line, and the (N+1)-th row may be an odd-numbered line. Alternatively, the N-th row may be an odd-numbered line, and the (N+1)-th row may be an even-numbered line. In the first embodiment, a potential change is inverted by applying a voltage to the lower layer electrodes connected together on a per even-numbered line basis and on a per odd-numbered line basis. It is illustrated that the potential of the electrode supplied with a constant voltage is set to be 7.5 V. However, since the potential may also be interpreted as substantially 0 V, the N line and the (N+1) line are alternately polarity inverted to be driven.

FIG. 22 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the first embodiment during the generation of an in-plane electric field. FIG. 23 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the first embodiment during the generation of a vertical electric field. FIG. 24 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the first embodiment during a initialization process step subsequent to the generation of the vertical electric field. FIG. 25 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the first embodiment during the generation of the in-plane electric field. FIG. 26 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the first embodiment during the generation of the vertical electric field. FIG. 27 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the first embodiment during the initialization process step subsequent to the generation of the vertical electric field.

As illustrated in FIG. 22 and FIG. 25, the liquid crystal is driven by the in-plane electric field between the pair of comb electrodes. As illustrated in FIG. 23 and FIG. 26, the comb electrodes and the lower layer electrode are set to be at 15 V or 0 V to apply the vertical electric field (all the TFTs are turned on a per even-numbered line basis and on a per odd-numbered line basis). As illustrated in FIG. 24 and FIG. 27, the TFT is turned off to set the pair of comb electrodes to be floating, or all the TFTs are turned on on a per even-numbered line basis and on a per odd-numbered line basis to set the pair of comb electrodes to 7.5 V and the lower layer electrode to 7.5 V. The liquid crystal layer is thus refreshed to the initial alignment (in the initial process step).

The liquid crystal display apparatus including the display crystal display panel of the first embodiment may include a member typically included in a standard liquid crystal display apparatus (such as a light source). The same is true of the embodiments to be discussed below.

Second Embodiment

FIG. 28 is a schematic sectional view of the liquid crystal display panel of a second embodiment. FIG. 29 is a plan view of a picture element in the liquid crystal display panel of the second embodiment. FIG. 30 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the second embodiment. FIG. 31 illustrates a potential change of each electrode in the liquid crystal display panel of the second embodiment.

In the driving method of each module of the second embodiment, one TFT is driven on a per picture element basis.

As illustrated in FIG. 28 through FIG. 31, a chain line with two dots denotes a wiring electrically connected to a lower layer electrode on the lower substrate. A chain line with one dot denotes a wiring electrically connected to one comb electrode of the pair of comb electrodes on the lower substrate. A wiring electrically connected to the other comb electrode of the pair of comb electrodes is denoted by the chain line with two dots because the other comb electrode of the pair of comb electrodes on the lower substrate is electrically connected to the lower layer electrode of the lower substrate. A broken line denotes a wiring electrically connected to the electrode on the upper substrate. Each of the lower layer electrodes also serves as a Cs electrode, and the lower layer electrodes are commonly connected on a per even-numbered line basis and on a per odd-numbered line basis.

In a picture element at an N-th row, a voltage applied to the lower layer electrode is 0 V during the light image displaying, and then changes to 15 V with the vertical electric field applied during the dark displaying (black image displaying) after becoming 7.5 V in the initialization process step (all TFTs turned on). In the initialization process step subsequent to the vertical electric field application, the voltage applied to the lower electrode is 7.5 V. In a picture element at an (N+1)-th row, a voltage applied to the lower layer electrode is 7.5 V during the light image displaying, then changes to 0 V with the vertical electric field applied during the dark displaying (black image displaying) after becoming 7.5 V in the initialization process step (all TFTs turned on). In the initialization process step subsequent to the vertical electric field application, the voltage applied to the lower electrode is 7.5 V. The N-th row may be an even-numbered line, and the (N+1)-th row may be an odd-numbered line. Alternatively, the N-th row may be an odd-numbered line, and the (N+1)-th row may be an even-numbered line. In the second embodiment, a potential change is inverted by applying a voltage to the lower layer electrodes connected together on a per even-numbered line basis and on a per odd-numbered line basis. It is illustrated that the potential of the electrode supplied with a constant voltage is set to be 7.5 V. However, since the potential may also be interpreted as substantially 0 V, the N line and the (N+1) line are alternately polarity inverted to be driven.

FIG. 32 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the second embodiment during the generation of an in-plane electric field. FIG. 33 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during an initialization process step subsequent to the generation of the in-plane electric field. FIG. 34 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during the generation of a vertical electric field. FIG. 35 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the second embodiment during an initialization process step subsequent to the generation of the vertical electric field. FIG. 36 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the second embodiment during the generation of the in-plane electric field. FIG. 37 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the initialization process step subsequent to the generation of the in-plane electric field. FIG. 38 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the generation of the vertical electric field. FIG. 39 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the second embodiment during the initialization process step subsequent to the generation of the vertical electric field.

As illustrated in FIG. 32 and FIG. 36, the liquid crystal is driven by the in-plane electric field between the pair of comb electrodes. As illustrated in FIG. 33 and FIG. 37, all the TFTs are turned on so that all the electrodes are reset to 7.5 V. As illustrated in FIG. 34 and FIG. 38, the TFT is turned off to set one comb electrode of the pair of comb electrodes to be floating, or all the TFTs are turned on on a per even-numbered line basis and on a per odd-numbered line basis to set one comb electrode of the pair of comb electrodes to 15 V or 0 V, and the lower layer electrode is set to 15 V or 0 V. The vertical electric field is thus applied. As illustrated in FIG. 35 and FIG. 39, the TFT is turned off to set one comb electrode of the pair of comb electrodes to be floating, or all the TFTs are turned on to set the pair of comb electrodes to 7.5 V, and the lower layer electrode is set to 7.5 V. The liquid crystal is thus refreshed to the initial alignment (in the initialization process step). The other reference numerals in the drawings related to the second embodiment result from adding 1 in hundreds place to the corresponding reference numerals in the first embodiment.

Modification of Second Embodiment

FIG. 40 is a schematic sectional view of the liquid crystal display panel of a modification of the second embodiment. FIG. 41 is a plan view of a picture element in the liquid crystal display panel of the modification of the second embodiment. FIG. 42 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the modification of the second embodiment. FIG. 43 illustrates a potential change of each electrode in the liquid crystal display panel of the modification of the second embodiment.

In the driving method of each module of the modification of the second embodiment, one TFT is driven on a per picture element basis.

As illustrated in FIG. 40 through FIG. 43, a chain line with two dots denotes a wiring electrically connected to a lower layer electrode on the lower substrate. A chain line with one dot denotes a wiring electrically connected to one comb electrode of the pair of comb electrodes on the lower substrate. A wiring electrically connected to the other comb electrode of the pair of comb electrodes is denoted by the chain line with two dots because the other comb electrode of the pair of comb electrodes on the lower substrate is electrically connected to the lower layer electrode of the lower substrate. A broken line denotes a wiring electrically connected to the electrode on the upper substrate. Each of the lower layer electrodes also serves as a Cs electrode, and the lower layer electrodes are commonly connected on a per even-numbered line basis and on a per odd-numbered line basis.

In a picture element at an N-th row, a voltage applied to the lower layer electrode is 0 V during the light image displaying, changes to 15 V during the dark displaying (black image displaying), and then changes to 7.5 V in the initialization process step for the dark displaying (black image displaying). In a picture element at an (N+1)-th row, a voltage applied to the lower layer electrode is 15 V during the light image displaying, changes to 0 V during the dark displaying (black image displaying), and then changes to 7.5 V in the initialization process step for the dark displaying (black image displaying). The N-th row may be an even-numbered line, and the (N+1)-th row may be an odd-numbered line. Alternatively, the N-th row may be an odd-numbered line, and the (N+1)-th row may be an even-numbered line. In the modification of the second embodiment, a potential change is inverted by applying a voltage to the lower layer electrodes connected together on a per even-numbered line basis and on a per odd-numbered line basis. It is illustrated that the potential of the electrode supplied with a constant voltage is set to be 7.5 V. However, since the potential may also be interpreted as substantially 0 V, the N line and the (N+1) line are alternately polarity inverted to be driven.

FIG. 44 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of a modification of the second embodiment during the generation of an in-plane electric field. FIG. 45 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of a vertical electric field. FIG. 46 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the modification of the second embodiment during an initialization process step subsequent to the generation of the vertical electric field. FIG. 47 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of the in-plane electric field. FIG. 48 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during the generation of the vertical electric field. FIG. 49 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the modification of the second embodiment during an initialization process step subsequent to the generation of the vertical electric field.

As illustrated in FIG. 44 and FIG. 47, the liquid crystal is driven by the in-plane electric field between the pair of comb electrodes. As illustrated in FIG. 45 and FIG. 48, the TFTs are turned on on a per even-numbered line basis and on a per odd-numbered line basis so that the vertical electric field is applied with the comb electrodes and the lower layer electrode set to 15 V or 0 V. As illustrated in FIG. 46 and FIG. 49, the TFT is turned off to set one comb electrode of the pair of comb electrodes to be floating, or all the TFTs are turned on to set the pair of comb electrodes to 7.5 V, and the lower layer electrode is set to 7.5 V. The liquid crystal is thus refreshed to the initial alignment (in the initialization process step). The other reference numerals in the drawings related to the modification of the second embodiment result from adding 1 in hundreds place to the corresponding reference numerals and then suffixing the corresponding reference numerals with an apostrophe (′) in the first embodiment.

Third Embodiment

FIG. 50 is a schematic sectional view of the liquid crystal display panel of a third embodiment. FIG. 51 is a plan view of a picture element in the liquid crystal display panel of the third embodiment. FIG. 52 is an equivalent circuit diagram of the picture element in the liquid crystal display panel of the third embodiment. FIG. 53 illustrates a potential change of each electrode in the liquid crystal display panel of the third embodiment.

In the driving method of each module of the third embodiment, one TFT is driven on a per picture element basis.

As illustrated in FIG. 50 through FIG. 53, a chain line with two dots denotes a wiring electrically connected to a lower layer electrode on the lower substrate. A chain line with one dot denotes a wiring electrically connected to one comb electrode of the pair of comb electrodes on the lower substrate. A wiring electrically connected to the other comb electrode of the pair of comb electrodes is denoted by the chain line with two dots because the other comb electrode of the pair of comb electrodes on the lower substrate is electrically connected to the lower layer electrode of the lower substrate. A broken line denotes a wiring electrically connected to the electrode on the upper substrate. Each of the lower layer electrodes also serves as a Cs electrode, and the lower layer electrodes are commonly connected on a per even-numbered line basis and on a per odd-numbered line basis. In the third embodiment, the opposite electrodes on the opposite substrate are also connected together on a per even-numbered line basis and on a per odd-numbered line basis.

In a picture element at an N-th row, a voltage applied to the lower layer electrode is 0 V during the light image displaying, and then changes to 15 V during the dark displaying (black image displaying). In a picture element at an (N+1)-th row, a voltage applied to the lower layer electrode is 15 V during the light image displaying, and then changes to 0 V during the dark displaying (black image displaying). In a picture element at the N-th row, a voltage applied to the opposite electrode on the side of the opposite substrate is 0 V during the light image displaying, then remains 0 V during the dark displaying (black image displaying), and then becomes 15 V in the initialization process step resulting in potential reversal. In a picture element at the (N+1)-th row, a voltage applied to the opposite electrode on the side of the opposite substrate is 15 V during the light image displaying, then remains 15 V during dark displaying (black image displaying), and then becomes 0 V in the initialization process step resulting in potential reversal. The N-th row may be an even-numbered line, and the (N+1)-th row may be an odd-numbered line. Alternatively, the N-th row may be an odd-numbered line, and the (N+1)-th row may be an even-numbered line. In the third embodiment, a voltage is applied to the lower layer electrodes and the opposite electrodes on the opposite substrate connected together on a per even-numbered line basis and on a per odd-numbered line basis, thereby reversing the potential change.

FIG. 54 is a schematic sectional view illustrating each electrode at an N-th row of the liquid crystal display panel of the third embodiment during the generation of an in-plane electric field. FIG. 55 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the third embodiment during the generation of a vertical electric field. FIG. 56 is a schematic sectional view illustrating each electrode at the N-th row of the liquid crystal display panel of the third embodiment during an initialization process step subsequent to the generation of the vertical electric field. FIG. 57 is a schematic sectional view illustrating each electrode at an (N+1)-th row of the liquid crystal display panel of the third embodiment during the generation of the in-plane electric field. FIG. 58 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the third embodiment during the generation of the vertical electric field. FIG. 59 is a schematic sectional view illustrating each electrode at the (N+1)-th row of the liquid crystal display panel of the third embodiment during the initialization process step subsequent to the generation of the vertical electric field.

As illustrated in FIG. 54 and FIG. 57, the liquid crystal is driven by the in-plane electric field between the pair of comb electrodes. As illustrated in FIG. 55 and FIG. 58, the TFTs are turned on on a per even-numbered line basis and on a per odd-numbered line basis to set the comb electrodes and the lower layer electrode together to 15 V or 0 V and to set the opposite electrode on the side of the opposite substrate to 0 V or 15 V to apply the vertical electric field. As illustrated in FIG. 56 and FIG. 59, the TFT is turned off to set one comb electrode of the pair of comb electrodes to be floating, or the TFTs are turned on on a per even-numbered line basis and on a per odd-numbered line basis to set one comb electrode of the comb electrodes to 15 V or 0 V. The opposites electrode on the opposite substrate and the lower layer electrode are set to 15 V or 0 V. The liquid crystal is thus refreshed to the initial alignment (in the initialization process step). The other reference numerals in the drawings related to the third embodiment result from adding 2 in hundreds place to the corresponding reference numerals in the first embodiment. The liquid crystal display panels of the first through third embodiments are easy to manufacture, and provide the fast response and high transmittance.

The above-described TFT driving method is performed during a period including a subframe period as a driving period extending until the liquid crystal is reverted back to the initial state. During the subframe period, the TFT driving method includes a driving operation to cause a potential difference between a pair of comb electrodes, a driving operation to cause a potential difference, higher than the potential difference between the pair of comb electrodes, between the opposite electrodes, and a driving operation to cause substantially no potential difference between all the electrodes of the pair of comb electrodes and the pair of opposite electrodes. In the embodiment, the driving operation to cause substantially no potential difference between all the electrodes of the pair of comb electrodes and the pair of opposite electrodes is performed subsequent to the driving operation to cause the potential difference, higher than the potential difference between the pair of comb electrodes, between the opposite electrodes. The alignment of the liquid crystal molecules is thus appropriately controlled, and the transmittance is sufficiently lowered during the black image displaying.

FIG. 60 is a schematic plan view illustrating a driving method of the liquid crystal display panel of the present invention. FIG. 60 illustrates a white image that is being written in the liquid crystal display panel. The voltages applied to the vertical lines connected to the sources of the TFTs are alternately inverted to write a white image. To write a black image, the voltages applied to the sources of the TFTs are not alternately inverted. As illustrated in FIG. 60, the gate bus lines are also alternately supplied with different voltages (two values of +35 V and −5 V). The lower layer electrodes are also alternately supplied with different voltages (three values of 7.5 V, 15 V, and 0 V). As illustrated in FIG. 60, a white image (intermediate tone of gradation) has already written on pixels along the top bus line, and a white displaying is thus maintained (image maintained 41). The lower layer electrode is continuously supplied with 7.5 V. The gate bus line is at a voltage of 35 V on the pixels 42 along a second bus line from the top, and a white image (intermediate tone of gradation) has been written. The lower layer electrode is also supplied with 7.5 V. A black image is written and maintained on the pixels 43 along a third bus line from the top. The lower layer electrode is supplied with 15 V. A black image is written and maintained on the pixels 43′ along a fourth bus line from the top. The lower layer electrode is supplied with 0 V. The opposite electrodes 23 always remain at 7.5 V.

FIG. 61 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention. FIG. 62 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention. FIG. 63 is a schematic plan view illustrating the driving operation of the liquid crystal display panel of the present invention. FIG. 64 is a schematic sectional view illustrating a liquid crystal display panel of the first comparative example during the generation of a fringe electric field. FIG. 65 is a schematic plan view illustrating the liquid crystal display panel of FIG. 64. FIG. 66 illustrates simulation results of the liquid crystal display panel of FIG. 64.

FIG. 61 illustrates a concept of the whole display panel on which the image writing of FIG. 60 is performed. In the image maintained 41, a data signal is applied and maintained. In the image written 42, the gate bus line is supplied with 35 V, the lower layer electrode is supplied with 7.5 V, and the data signal is applied. In the black image maintained 43, the image writing is not yet performed.

FIG. 62 and FIG. 63 illustrate concepts of the whole display panel on which the black image writing is performed. As illustrated in FIG. 62, a black image is written on the lines at a time without voltage alternating. In this way, a write speed becomes higher. As illustrated in FIG. 63, the alternating application of voltage is performed as the image writing, and thus a black image is written. The lower layer electrodes may be alternately supplied with 15 V and 0 V on a line-by-line basis or on a frame-by-frame basis.

In each of the embodiments, the liquid crystal display panel is easy to manufacture, and achieves high transmittance. The field sequential method can also be implemented on the liquid crystal display panel. The transmittance high enough to be applied for on-board applications and 3D display apparatus applications is achieved. Among the applications, a liquid crystal driving apparatus works on the field sequential driving, and preferably includes a circularly polarizing plate. When the field sequential driving is performed, internal reflections intensify because no color filter is used. The transmittance of a color filter is typically ⅓, and reflected light passes through the color filter twice, and the internal reflection with the color filter used is reduced to be as high as 1/10. For this reason, the use of the circularly polarizing plate can sufficiently reduce the internal reflection. The electrode structure of the TFT substrate and the opposite substrate in the liquid crystal display panel and the liquid crystal display apparatus of the present invention is checked through a microscopic observation using an SEM (Scanning Electrode Microscope) or the like.

First Comparative Example

FIG. 64 is a schematic sectional view illustrating a liquid crystal display panel of the first comparative example during the generation of a fringe electric field. FIG. 65 is a schematic plan view illustrating the liquid crystal display panel of FIG. 64. FIG. 66 illustrates simulation results of the liquid crystal display panel of FIG. 64.

The liquid crystal display panel of the first comparative example generates the fringe electric field through the FFS driving in the same way as described in PTL 1. FIG. 66 illustrates simulation results of a director, electric field, and transmittance distribution (a cell thickness of 5.4 μm and a comb tooth spacing of 2.6 μm). The reference numerals of the first comparative example of FIG. 64 result from adding 3 in hundreds place to the corresponding reference numerals in the first embodiment.

As illustrated in FIG. 64, a slit electrode is set to 14 V, and a planar opposite electrode is set to 7 V. Alternatively, for example, the slit electrode is set to 5 V, and the planar opposite electrode is set to 0 V. In the display of the FFS driving of PTL 1 (the slit electrode is used instead of the pair of comb electrodes), liquid crystal molecules are rotated using the fringe electric field generated between an upper layer electrode and a lower layer electrode on the lower substrate. Since only the liquid crystal molecules in the vicinity of the slit electrode rotate, the transmittance in simulation was as low as 3.6%. Increasing the transmittance to a level described with reference to the embodiments was difficult (see FIG. 66).

Second Comparative Example

FIG. 67 is a graph illustrating a response waveform obtained through simulation of comb driving in a TN mode of a second comparative example. Since no driving is performed for an initial duration of 0.4 ms, a rise period (a vertical electric field period) is 2.4 ms, and a fall period (an in-plane electric field) is 1.6 ms.

FIG. 68 through FIG. 70 illustrate simulation results of the liquid crystal display panel of the second comparative example. More specifically, FIG. 68 illustrates the simulation results of the director D, the electric field, and the transmittance distribution at a time point of 2.6 ms. FIG. 69 illustrates the simulation results of the director D, the electric field, and the transmittance distribution at a time point of 4.2 ms. FIG. 70 illustrates the simulation results of the director D, the electric field, and the transmittance distribution at a time point of 5.6 ms. As illustrated in FIG. 67, no driving is performed for the initial duration of 0.4 ms. A plot of a solid line denotes the transmittance. The director D denotes an alignment direction of the long axis of the liquid crystal molecules. In the second comparative example, the comb electrode and TN mode described in PTL 2 were used. A simulation performed using LCD MASTER 2D revealed that the second comparative example failed to provide the effect of fast response. The simulation condition was a cell thickness of 5.4 μm and a comb tooth spacing of 2.6 μm. As illustrated in FIG. 68, the liquid crystal molecules respond vertically to the vertical electric field at the time point of 2.6 ms. Although liquid crystal molecules between comb electrodes are horizontally aligned in response to the in-plane electric field at the time point of 4.2 ms as illustrated in FIG. 69, liquid crystal molecules above comb electrode do not respond and thus remain vertically aligned by the vertical electric field between the lower substrate and the upper substrate. Since the alignment of the liquid crystal molecules is disturbed by the in-plane electric field, the liquid crystal molecules will not be aligned to the initial alignment at time point of 5.6 ms even if the initialization process step is performed as illustrated in FIG. 70. The results of the second comparative example revealed that the use of the comb electrode and TN mode described in PTL 2 fails to achieve the effect of the fast response.

FIG. 73 is a schematic plan view illustrating an example of a thin-film transistor used for a pixel electrode of a liquid crystal display panel of the present invention. Let S represent a source, D represent a drain, and G represent a gate.

The semiconductor of the thin-film transistor for use in the pixel electrode of the present invention is preferably an oxide semiconductor (indium gallium zinc oxide (IGZO) or the like). FIG. 73 illustrates the thin-film transistor manufactured of Si semiconductor. IGZO may be appropriately used for a semiconductor layer instead of Si semiconductor. The oxide semiconductor exhibits a higher carrier mobility than amorphous silicon. In this way, a ratio of an area per pixel occupied by the oxide semiconductor transistor is smaller than that occupied by the amorphous silicon transistor. More specifically, miniaturization may be performed by 40% to 50%.

Miniaturization directly contributes to increasing an aperture ratio, and transmittance per pixel is thus increased. The use of the oxide semiconductor TFT substantially promotes the transmittance increasing effects as one of the advantageous effects of the present invention.

Mobile terminals (such as a tablet or a smartphone) featuring high resolution have typically a resolution of 300 ppi (pixel per inch), and this level of resolution is interpreted as a pixel pitch of 30 μm. The combination of the above-described liquid crystal modes of the present invention and an increase in the aperture ratio resulting from the use of IGZO TFT produces a synergistic effect in the improvement of the transmittance performance.

Given the pixels of 35 μm pitch, the use of IGZO TFT reduces the area of the TFT, thereby increasing the aperture ratio by 5% (transmittance) as illustrated in Table 3. In Table 3, L (μm) indicates a length in FIG. 73, and W (μm) indicates a length in FIG. 3. An area (μm2) indicates the area of the TFT. The aperture ratio is an area ratio of the area of an aperture to pixel.

TABLE 3 35 μm pitch α-Si IGZO L (μm) 4 4 W (μm) 9 5 Area (μm2) 235 100 Aperture ratio (%) 55 60

The number of pixels increases as image resolution increases. High-speed writing is thus needed in high-speed driving. The oxide semiconductor featuring a higher carrier mobility is advantageous in the high-speeding writing.

More specifically, the use of the combination of the liquid crystal mode of the present invention and the oxide semiconductor TFT gives performance much more higher than the liquid crystal panel manufactured of a conventional amorphous TFT.

The examples of the embodiments may be appropriately combined as long as the combination fall within the scope of the present invention.

This application is based on Japanese Unexamined Patent Application Publication No. 2011-061662 filed Mar. 18, 2011, and Japanese Unexamined Patent Application Publication No. 2011-142351 filed Jun. 27, 2011, and claims priority under Paris Convention or the rule of a designated state. The contents of those applications are incorporated by reference in this application in its entirety.

REFERENCE SIGNS LIST

  • 10, 110, 110′, 210, 410, and 510: Array substrates
  • 11, 21, 411, 421, 511, and 521: Glass substrates
  • 13, 23, 113, 113′, 123, 213, 223, 313, 323, 413, 423, 513, and 523: Opposite electrodes
  • 15, 415, and 515: Insulating layers
  • 16: Pair of comb electrodes
  • 17, 19, 117, 117′, 119, 119′, 217, 219, 417, 419, 517, and 519: Comb electrodes
  • 20, 120, 120′, 220, 420, and 520: Opposite substrates
  • 30, 130, 130′, 230, 430, and 530: Liquid crystal layers
  • 31: Liquid crystal (liquid crystal molecules)
  • 41 and 63: Image maintained
  • 42: Image written
  • 43, 43′, 61, and 61′: Black image maintained
  • 51 and 62: Black image written
  • Si: Si semiconductor
  • S: Source
  • D: Drain
  • G: Gate

Claims

1. A liquid crystal display panel comprising a first substrate, a second substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate,

wherein each of the first substrate and the second substrate includes electrodes,
wherein the electrodes of the second substrate include a pair of comb substrates and a planar electrode, and
wherein the liquid crystal display panel is configured to align liquid crystal molecules in the liquid crystal layer in a direction horizontal to a substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate.

2. The liquid crystal display panel according to claim 1, wherein the liquid crystal layer comprises liquid crystal molecules that align in a direction vertical to the substrate main surface during a no-voltage application period.

3. The liquid crystal display panel according to claim 1, wherein the pair of comb electrodes are arranged on a common layer.

4. The liquid crystal display panel according to claim 1, wherein potentials of the electrodes of the pair of comb electrodes are different from each other in a potential range equal to or above a threshold voltage.

5. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is configured to align the liquid crystal molecules in the liquid crystal layer in a direction vertical to the substrate main surface in response to an electric field generated between the pair of comb electrodes or an electric field generated between the first substrate and the second substrate.

6. The liquid crystal display panel according to claim 1, wherein the electrode of the first substrate is a planar electrode.

7. The liquid crystal display panel according to claim 1, wherein the liquid crystal layer comprises liquid crystal molecules having a positive dielectric anisotropy.

8. The liquid crystal display panel according to claim 1, wherein the liquid crystal layer comprises liquid crystal molecules having a negative dielectric anisotropy.

9. The liquid crystal display panel according to claim 1, wherein planar electrodes on the second substrate are electrically connected together along a pixel line.

10. A liquid crystal display apparatus comprising the liquid crystal display panel according to claim 1.

Patent History
Publication number: 20140016075
Type: Application
Filed: Sep 18, 2013
Publication Date: Jan 16, 2014
Applicant: SHARP KABUSHIKI KAISHA (Osaka)
Inventors: Yosuke IWATA (Osaka-shi), Mitsuhiro MURATA (Osaka-shi), Hiroaki ASAGI (Osaka-shi), Yasuhiro NASU (Osaka-shi), Hidefumi YOSHIDA (Osaka-shi)
Application Number: 14/030,155
Classifications
Current U.S. Class: Interdigited (comb-shaped) Electrodes (349/141)
International Classification: G02F 1/1343 (20060101);