Patents by Inventor Yasuhiro Nishimori
Yasuhiro Nishimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080216865Abstract: The invention provides a plasma processing method capable of reducing particle caused by flinging up of particles by airflow due to the pressure fluctuation in the processing chamber during the time the sample is carried into the processing chamber, subjected to plasma processing and carried out of the processing chamber.Type: ApplicationFiled: August 6, 2007Publication date: September 11, 2008Inventors: Masunori Ishihara, Masamichi Sakaguchi, Yasuhiro Nishimori, Yutaka Kudou, Satoshi Une
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Publication number: 20070090090Abstract: A surface treatment method is provided, wherein the ratio of the etching rate of a lower resist of a multilayer resist film used for forming a fine pattern to that of an inorganic intermediate layer thin film serving as a mask to control the dimension of the pattern, that is, the shoulder selection ratio, is increased in an etching treatment of a semiconductor or the like. In the surface treatment method of a semiconductor, in which an inorganic intermediate film and an upper resist film are laminated on a lower resist film, by using plasma, CO2 containing oxygen as a primary component is added to a gas composed of nitrogen and hydrogen, so that an etching gas is prepared. Consequently, cutting of a shoulder of the inorganic intermediate layer film is reduced and a perpendicular shape is attained.Type: ApplicationFiled: February 2, 2006Publication date: April 26, 2007Inventors: Koichi Nakaune, Yasuhiro Nishimori, Toshiaki Nishida, Tsuyoshi Yoshida
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Publication number: 20070023683Abstract: A vacuum processing apparatus and method includes a sample taken out from a given cassette placed on a cassette support in atmosphere, the sample is carried into a vacuum processing chamber via a chamber enabling switching between atmosphere and vacuum, the sample is subjected to etching processing in the vacuum processing chamber, and at least one inspection process is carried out in the vacuum either before or after etching of the sample in the vacuum processing chamber. The at least one inspection process in the vacuum is a defect inspection.Type: ApplicationFiled: September 12, 2006Publication date: February 1, 2007Inventors: Yoshitaka Kai, Kenichi Kuwabara, Takeo Uchino, Yasuhiro Nishimori, Takeshi Oono, Takeshi Shimada
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Patent number: 7112805Abstract: The invention provides a semiconductor fabrication apparatus capable of preventing increase of carriage time of samples, deterioration of sample output, increase of footprint and increase of investment costs. The vacuum processing apparatus comprises a plurality of vacuum processing chambers for subjecting a sample to vacuum processing; a vacuum carriage for carrying the sample into and out of the vacuum processing chamber; a switchable chamber capable of being switched between atmosphere and vacuum for carrying the sample into and out of the vacuum processing chamber; a cassette support for supporting a plurality of cassettes and a controller for controlling carrying of the sample from a cassette through the switchable chambers, the vacuum carriage means into and out of the vacuum processing chamber. The vacuum processing chamber is equipped with an etching chamber and a critical dimension measurement chamber for critical dimension inspection of the sample.Type: GrantFiled: June 25, 2004Date of Patent: September 26, 2006Assignee: Hitachi High-Technologies CorporationInventors: Yoshitaka Kai, Kenichi Kuwabara, Takeo Uchino, Yasuhiro Nishimori, Takeshi Oono, Takeshi Shimada
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Patent number: 7049243Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: GrantFiled: January 12, 2004Date of Patent: May 23, 2006Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20060016781Abstract: The object of the invention is to provide a dry etching method for processing the edge portion of a hard mask to have a round profile. The present method for manufacturing a semiconductor device comprises (b) forming a silicon nitride film 12 mask using a patterned photoresist 13, (c) cutting back the photoresist 13 via dry etching, and (d) etching the exposed edge portion of the silicon nitride film mask 12, to thereby enable trench processing using a silicon nitride film mask 12 having a rounded edge portion.Type: ApplicationFiled: August 30, 2004Publication date: January 26, 2006Inventors: Kenichi Kuwabara, Yasuhiro Nishimori, Masunori Ishihara, Satoshi Une
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Publication number: 20050218337Abstract: The invention provides a semiconductor fabrication apparatus capable of preventing increase of carriage time of samples, deterioration of sample output, increase of footprint and increase of investment costs.Type: ApplicationFiled: June 25, 2004Publication date: October 6, 2005Inventors: Yoshitaka Kai, Kenichi Kuwabara, Takeo Uchino, Yasuhiro Nishimori, Takeshi Oono, Takeshi Shimada
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Patent number: 6946847Abstract: An impedance matching device is provided, for which the electric characteristics at an output terminal are accurately analyzed. The matching device is provided with an input detector for detecting RF voltage and current at the input terminal, and an output detector for detecting RF voltage outputted from the output terminal. The matching device also includes a controller for achieving impedance matching between a high frequency power source connected to the input terminal and a load connected to the output terminal. The impedance matching is performed by adjusting variable capacitors based on the detection data supplied from the input detector. When the impedance of the power source is matched to that of the load, the controller calculates the output impedance, RF voltage and RF current at the output terminal, based on the adjusted capacitances of the capacitors, a pre-obtained reactance-impedance data and the detection data supplied from the output detector.Type: GrantFiled: January 30, 2003Date of Patent: September 20, 2005Assignee: Daihen CorporationInventors: Yasuhiro Nishimori, Shuji Omae, Masakatsu Mito, Yuji Ishida, Koji Itadani
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Publication number: 20040259361Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.Type: ApplicationFiled: January 12, 2004Publication date: December 23, 2004Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6677244Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: GrantFiled: May 1, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20030184319Abstract: An impedance matching device is provided, for which the electric characteristics at an output terminal are accurately analyzed. The matching device is provided with an input detector for detecting RF voltage and current at the input terminal, and an output detector for detecting RF voltage outputted from the output terminal. The matching device also includes a controller for achieving impedance matching between a high frequency power source connected to the input terminal and a load connected to the output terminal. The impedance matching is performed by adjusting variable capacitors based on the detection data supplied from the input detector. When the impedance of the power source is matched to that of the load, the controller calculates the output impedance, RF voltage and RF current at the output terminal, based on the adjusted capacitances of the capacitors, a pre-obtained reactance-impedance data and the detection data supplied from the output detector.Type: ApplicationFiled: January 30, 2003Publication date: October 2, 2003Applicant: DAIHEN CORPORATIONInventors: Yasuhiro Nishimori, Shuji Omae, Masakatsu Mito, Yuji Ishida, Koji Itadani
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Patent number: 6492277Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.Type: GrantFiled: September 10, 1999Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Publication number: 20020123229Abstract: A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.Type: ApplicationFiled: May 1, 2002Publication date: September 5, 2002Inventors: Tetsuo Ono, Yasuhiro Nishimori, Takashi Sato, Naoyuki Kofuji, Masaru Izawa, Yasushi Goto, Ken Yoshioka, Hideyuki Kazumi, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takafumi Tokunaga, Motohiko Yoshigai
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Patent number: 6291999Abstract: A plasma monitoring apparatus for monitoring a condition of plasma of a plasma load to which power is supplied from a high frequency power source through an impedance matcher provides with a first input impedance calculator for calculating an impedance as a first input impedance from a supply-side terminal of the matcher to the plasma load-side based on voltage, current and phase difference detected at the supply-side terminal of the matcher, a second input impedance calculator for calculating an impedance as a second input impedance from a load-side terminal of the matcher to the plasma load based on a impedance of a element of the matcher and the first input impedance and a plasma impedance calculator for calculating an impedance of the plasma load from the second input impedance and an impedance of a supply-side connecting the matcher and the plasma load.Type: GrantFiled: September 30, 1998Date of Patent: September 18, 2001Assignee: Daihen Corp.Inventors: Yasuhiro Nishimori, Michio Taniguchi, Kazuki Kondo