Patents by Inventor Yasuhiro Shimamoto
Yasuhiro Shimamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130341727Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.Type: ApplicationFiled: July 18, 2013Publication date: December 26, 2013Applicant: Renesas Electronics CorporationInventors: Yasuhiro SHIMAMOTO, Jiro YUGAMI, Masao INOUE, Masaharu MIZUTANI
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Publication number: 20130234163Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.Type: ApplicationFiled: March 29, 2011Publication date: September 12, 2013Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
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Publication number: 20130234236Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.Type: ApplicationFiled: March 17, 2013Publication date: September 12, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Itaru YANAGI, Toshiyuki MINE, Hirotaka HAMAMURA, Digh HISAMOTO, Yasuhiro SHIMAMOTO
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Patent number: 8501558Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.Type: GrantFiled: January 11, 2011Date of Patent: August 6, 2013Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
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Publication number: 20130140622Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: ApplicationFiled: January 31, 2013Publication date: June 6, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Patent number: 8410543Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.Type: GrantFiled: December 27, 2007Date of Patent: April 2, 2013Assignee: Renesas Electronics CorporationInventors: Itaru Yanagi, Toshiyuki Mine, Hirotaka Hamamura, Digh Hisamoto, Yasuhiro Shimamoto
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Patent number: 8409949Abstract: Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).Type: GrantFiled: June 23, 2010Date of Patent: April 2, 2013Assignee: Renesas Electronics CorporationInventors: Tsuyoshi Arigane, Digh Hisamoto, Yasuhiro Shimamoto, Toshiyuki Mine
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Patent number: 8390053Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.Type: GrantFiled: August 8, 2008Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasufumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
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Patent number: 8385124Abstract: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.Type: GrantFiled: March 29, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Tsuyoshi Arigane, Digh Hisamoto, Yasuhiro Shimamoto, Yutaka Okuyama
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Patent number: 8319274Abstract: A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.Type: GrantFiled: July 27, 2007Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Itaru Yanagi, Yasuhiro Shimamoto, Toshiyuki Mine, Yutaka Okuyama
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Publication number: 20120217513Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.Type: ApplicationFiled: January 12, 2012Publication date: August 30, 2012Inventors: Naoki TEGA, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
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Patent number: 8125012Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.Type: GrantFiled: December 15, 2006Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Mine, Kan Yasui, Tetsuya Ishimaru, Yasuhiro Shimamoto
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Patent number: 8063433Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.Type: GrantFiled: April 24, 2008Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
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Publication number: 20110242888Abstract: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.Type: ApplicationFiled: March 29, 2011Publication date: October 6, 2011Inventors: Tsuyoshi ARIGANE, Digh Hisamoto, Yasuhiro Shimamoto, Yutaka Okuyama
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Publication number: 20110235419Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.Type: ApplicationFiled: March 28, 2011Publication date: September 29, 2011Inventors: Tetsuya ISHIMARU, Yasuhiro Shimamoto, Hideo Kasai, Yutaka Okuyama, Tsuyoshi Arigane
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Publication number: 20110111566Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.Type: ApplicationFiled: January 11, 2011Publication date: May 12, 2011Inventors: Yasuhiro SHIMAMOTO, Jiro Yugami, Masao Inoue, Masaharu Mizutani
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Patent number: 7935597Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: October 26, 2010Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7915666Abstract: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.Type: GrantFiled: May 20, 2008Date of Patent: March 29, 2011Assignee: Renesas Electronics CorporationInventors: Kan Yasui, Tetsuya Ishimaru, Digh Hisamoto, Yasuhiro Shimamoto
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Patent number: 7915686Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.Type: GrantFiled: May 24, 2006Date of Patent: March 29, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
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Publication number: 20110039385Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Inventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura