Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.

Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.

Abstract: A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.

Abstract: A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

Abstract: In the method of manufacturing a semiconductor device according to this invention, when an interlayer insulating film is fabricated such that an opening is cylindrical and low-pressure and long-throw sputtering is used for forming a lower ruthenium electrode, a ruthenium film can be deposited on the side wall of a deep hole. Further, after removing the ruthenium film deposited on the upper surface of the interlayer insulating film, a dielectric material comprising, for example, a tantalum pentoxide film is deposited. Successively, an upper ruthenium electrode is deposited using, for example, Ru(EtCp)2 as a starting material and by chemical vapor deposition of conveying the starting material by bubbling. The upper ruthenium electrode can be formed with good coverage by using conditions that the deposition rate of the ruthenium film depends on the formation temperature (reaction controlling condition). This invention can provide a fine concave type capacitor having a ruthenium electrode.

Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: Disclosed are a semiconductor device which hardly experiences a reduction in mobility caused by scattering by the fixed charge existent in a gate insulating film while the EOT of a fine CMOS comprising the high-dielectric gate insulating film is reduced and which enables high integration, and a production process therefor. CMOS having no junction is formed on an SOI substrate and a high-dielectric gate insulating film is used as the gate insulating film of the CMOS. The feature of the CMOS device of the present invention is that the CMOS device is operated in an accumulation mode. Since a channel is formed several nm away from the surface of the substrate as compared with an ordinary device which operates in an inversion mode, a reduction in mobility caused by the fixed charge existent in the gate insulating film can be reduced.

Abstract: A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.

Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N20 atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm−2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm−2 or more.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

Abstract: A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

Abstract: A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.