Patents by Inventor Yasuhiro Shimura

Yasuhiro Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210333731
    Abstract: A heater of the present invention includes jointed heat generating resistors having a positive temperature characteristic of resistance and provided between a first conductive element and a second conductive element on a substrate in a longitudinal direction of the substrate, and a plurality of heating blocks provided in the longitudinal direction, each of which is a set of the first conductive element, the second conductive element, and the heat generating resistor, and power supplied to at least one of the plurality of heating blocks can be controlled independent of other heating blocks.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventor: Yasuhiro Shimura
  • Patent number: 11156946
    Abstract: In a heater including a plurality of first temperature detection elements that are arranged at predetermined intervals in a longitudinal direction of a substrate and respectively output temperature signals individually, and a plurality of second temperature detection elements that are arranged at predetermined intervals in positions that differ from the positions of the first temperature detection elements in a lateral direction that is orthogonal to the longitudinal direction but correspond to the positions of at least some of the plurality of first temperature detection elements in the longitudinal direction, and that output a single temperature signal obtained by adding individual temperature signals together, the individual temperature signals included in the single temperature signal are acquired on the basis of the plurality of temperature signals output by the plurality of first temperature detection elements and the single temperature signal.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: October 26, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryota Ogura, Yasuhiro Shimura
  • Publication number: 20210296340
    Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhiro SHIMURA
  • Publication number: 20210295919
    Abstract: A semiconductor storage device includes first and second memory strings, a word line, first and second select gate lines, and a control circuit. The first memory string includes a first memory transistor and a first select transistor. The second memory string includes a second memory transistor and a second select transistor. The word line is connected to the first and second memory transistors. The control circuit is connected to the word line and the first and second select gate lines. The control circuit is configured to perform, during a write sequence, a program operation on each of the first and second memory transistors in turn and a verify operation on only one of the first and second memory transistors.
    Type: Application
    Filed: August 27, 2020
    Publication date: September 23, 2021
    Inventor: Yasuhiro SHIMURA
  • Patent number: 11079705
    Abstract: A heater of the present invention includes jointed heat generating resistors having a positive temperature characteristic of resistance and provided between a first conductive element and a second conductive element on a substrate in a longitudinal direction of the substrate, and a plurality of heating blocks provided in the longitudinal direction, each of which is a set of the first conductive element, the second conductive element, and the heat generating resistor, and power supplied to at least one of the plurality of heating blocks can be controlled independent of other heating blocks.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 3, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuhiro Shimura
  • Publication number: 20210200130
    Abstract: In an image heating device having a plurality of heating blocks which are controllable independently in a longitudinal direction of a heater, an increase of the size of the heater can be suppressed, and temperatures of a plurality of heating block can be detected. A heater has a first temperature sensor corresponding to a first heating block, a second temperature sensor corresponding to a second heating block, a first electric conductor electrically coupled to the first temperature sensor, a second electric conductor electrically coupled to the second temperature sensor, and a common electric conductor electrically coupled to the first and second temperature sensors.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 1, 2021
    Inventors: Yasuhiro Shimura, Akira Kato, Atsushi Iwasaki
  • Patent number: 11049867
    Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhiro Shimura
  • Publication number: 20210193239
    Abstract: A semiconductor storage device includes memory cells a controller performing a write operation on the memory cells. The write operation includes program loops with a program operation and a verification operation. In a first loop the controller applies a first program voltage and a first verification voltage. Next, a detection operation counts the memory cells with a threshold voltage above a first threshold value. In a second program loop, after the detection operation, the controller applies a second program voltage and a second verification voltage. The values of used for second program voltage and the second verification voltage are set dependent on the counted number of memory cells with a threshold voltage above the first threshold value.
    Type: Application
    Filed: September 3, 2020
    Publication date: June 24, 2021
    Inventors: Shinji SUZUKI, Yasuhiro SHIMURA
  • Patent number: 10983463
    Abstract: In an image heating device having a plurality of heating blocks which are controllable independently in a longitudinal direction of a heater, an increase of the size of the heater can be suppressed, and temperatures of a plurality of heating block can be detected. A heater has a first temperature sensor corresponding to a first heating block, a second temperature sensor corresponding to a second heating block, a first electric conductor electrically coupled to the first temperature sensor, a second electric conductor electrically coupled to the second temperature sensor, and a common electric conductor electrically coupled to the first and second temperature sensors.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 20, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Shimura, Akira Kato, Atsushi Iwasaki
  • Publication number: 20210091116
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhiro SHIMURA
  • Patent number: 10955778
    Abstract: An image forming apparatus includes a heater including a heating element, a driving unit that supplies electrical power to the heating element, and a plurality of temperature detection portions, each detecting a temperature of the heater, and being disposed on a first circuit. A control unit controls the driving unit based on the temperatures detected by the plurality of temperature detection portions, the control unit being disposed on a second circuit, which is isolated from the first circuit. A plurality of abnormality detection circuit portions output signals corresponding to the temperatures detected by the plurality of temperature detection portions, and are disposed on the first circuits. In addition, an abnormality transmission circuit portion transmits a signal indicating an abnormality in the heater to the control unit based on the signals output by the abnormality detection circuit portions.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 23, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Saito, Ryota Ogura, Yasuhiro Shimura
  • Publication number: 20210074359
    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Kenrou KIKUCHI, Yasuhiro SHIMURA
  • Patent number: 10915051
    Abstract: The image forming apparatus is characterized in that information about an input voltage detected on the primary side of a transformer is transmitted from a primary-side switching control unit to a secondary-side controller for controlling a heating device, and the controller controls the temperature of a heater of the heating device based on the transmitted information.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Izaki, Yasuhiro Shimura
  • Patent number: 10886297
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhiro Shimura
  • Publication number: 20200341417
    Abstract: Provided is an image forming apparatus including a temperature sensing circuit to which a temperature sensing element is electrically connected, wherein a surface of a heater on a side where the temperature sensing element is provided is in contact with the inner surface of a film, a heating element is provided in a primary side circuit which is electrically connected to a commercial power supply, and the temperature sensing circuit is electrically insulated from both of the primary side circuit and a secondary side circuit which is electrically insulated from the primary side circuit.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Yasuhiro Shimura, Yusuke Saito, Ryota Ogura
  • Patent number: 10803950
    Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
  • Patent number: 10783975
    Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
  • Publication number: 20200273530
    Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.
    Type: Application
    Filed: September 5, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
  • Patent number: 10755786
    Abstract: A semiconductor memory device according to an embodiment includes a plurality of strings each including a select transistor and a memory cell that can be set to any one of a plurality of different threshold voltages, a select gate line that is commonly connected to the select transistors of the plurality of strings, a plurality of bit lines that are individually connected to the plurality of strings, a word line that is commonly connected to the memory cells of the plurality of strings, and a control unit configured to execute a write sequence for repeatedly performing a plurality of loops each including a set of a program operation and a verify operation, and a voltage applied to the select gate line in the program operation of a last loop is lower than a voltage applied to the select gate line in the program operation of a first loop.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Yoshikazu Harada
  • Patent number: 10747151
    Abstract: Provided is an image forming apparatus including a temperature sensing circuit to which a temperature sensing element is electrically connected, wherein a surface of a heater on a side where the temperature sensing element is provided is in contact with the inner surface of a film, a heating element is provided in a primary side circuit which is electrically connected to a commercial power supply, and the temperature sensing circuit is electrically insulated from both of the primary side circuit and a secondary side circuit which is electrically insulated from the primary side circuit.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Shimura, Yusuke Saito, Ryota Ogura