Patents by Inventor Yasuhiro Shimura

Yasuhiro Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power supply apparatus and image forming apparatus switching a capacitance value of a resonance capacitor at a time of a continuous operation and an intermittent operation
    Patent number: 10389259
    Abstract: The power supply apparatus switches the capacitance of a resonance capacitor to a first value at the time of a continuous operation, and switches the capacitance of the resonance capacitor to a second value smaller than the first value at the time of an intermittent operation.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 20, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Asano, Yasuhiro Shimura
  • Memory device and memory controller
    Patent number: 10347338
    Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190198527
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhiro SHIMURA
  • Power supply apparatus and image forming apparatus controlling a turn-on duty of a switching element for switching a voltage state
    Patent number: 10320299
    Abstract: The power supply apparatus includes a control unit configured to perform control of gradually changing a turn-on duty of a first switching element when a first voltage mode is switched to a second voltage mode or when the second voltage mode is switched to the first voltage mode.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 11, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • IMAGE FORMING APPARATUS
    Publication number: 20190155199
    Abstract: An image forming apparatus includes a driving unit that supplies electric power to a heating element of a heater; a plurality of temperature detection portion disposed on a first potential side to detect temperatures of the heater; a control unit that is disposed on a second potential side isolated from the first potential side to control the driving unit on the basis of the temperatures detected by the temperature detection portion; a plurality of abnormality detection circuit portions disposed on the first potential side to output signals corresponding to detection results obtained by the plurality of temperature detection portion; and an abnormality transmission circuit portion that transmits an abnormality in the heater to the control unit on the basis of at least one of the signals output by the plurality of abnormality detection circuit portions.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 23, 2019
    Inventors: Yusuke Saito, Ryota Ogura, Yasuhiro Shimura
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190149054
    Abstract: The power supply apparatus includes a transformer, at least one switching element provided on a primary side of the transformer and configured to perform a switching operation to output an output voltage from a secondary side of the transformer, and a control unit configured to determine a turn-on time of a pulse signal for controlling the switching element for each of first cycles, and perform a predetermined control in which a change value of the turn-on time of the pulse signal for each of second cycles each including the first cycles becomes smaller than a change value of the turn-on time of the pulse signal for each of the first cycles, to change the second cycle depending on operation states.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 16, 2019
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • Semiconductor memory device and method of manufacturing the same
    Patent number: 10263008
    Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Nishida, Katsuyuki Sekine, Hirokazu Ishigaki, Yasuhiro Shimura
  • Semiconductor memory device
    Patent number: 10262703
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, a first word line electrically coupled to the first memory cell, a second word line electrically coupled to the second memory cell, and a control circuit configured to supply voltages to the first word line and the second word line. In a read, the control circuit applies a first voltage to the first word line and a second voltage to the second word line, applies, after applying the first voltage to the first word line and the second voltage to the second word line, a third voltage lower than the first voltage and the second voltage to the second word line, and applies, after applying the third voltage to the second word line, the third voltage to the first word line.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Keita Kimura
  • Semiconductor memory device
    Patent number: 10255979
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190098159
    Abstract: The power supply apparatus includes a transformer, a switching unit provided on a primary side of the transformer and configured to perform switching operation for converting an input voltage resulting from rectification and smoothing of an AC voltage and outputting an output voltage from a secondary side of the transformer; a first detection unit configured to detect the output voltage, a feedback unit configured to generate a feedback voltage based on the voltage detected by the first detection unit; a control unit configured to control the switching operation of the switching unit based on the feedback voltage generated by the feedback unit; and a second detection unit configured to detect the AC voltage.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Inventors: Hiroki Asano, Yasuhiro Shimura
  • Semiconductor memory device having a laminated body including a plurality of control gate electrodes laminated in a first direction
    Patent number: 10242998
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Shimura
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190088663
    Abstract: A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 21, 2019
    Inventors: Go SHIKATA, Yasuhiro SHIMURA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190088342
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhiro SHIMURA, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190058406
    Abstract: The power supply apparatus switches the capacitance of a resonance capacitor to a first value at the time of a continuous operation, and switches the capacitance of the resonance capacitor to a second value smaller than the first value at the time of an intermittent operation.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 21, 2019
    Inventors: Hiroki Asano, Yasuhiro Shimura
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190058387
    Abstract: The power supply apparatus includes a current detection unit configured to detect a current that flows through a first switching element of a transformer, and a control unit controls a turn-on time of the first switching element based on a feedback voltage from a secondary side of the transformer, controls a turn-on time of a second switching element based on a detection result of the current detection unit, and performs switching between a continuous control and an intermittent control based on the feedback voltage, the continuous control being a control to perform an operation of continuing a first period, the intermittent control being a control to perform an operation of alternately repeating the first period and a second period.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 21, 2019
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190058386
    Abstract: The power supply apparatus alternately repeats a control between a first control of varying a frequency of switching operation within a predetermined range and for a predetermined cycle according to a frequency determined based on a feedback voltage, and a second control of varying the frequency within a range narrower than the predetermined range or a third control of controlling the frequency to be a constant frequency.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 21, 2019
    Inventor: Yasuhiro Shimura
  • POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS
    Publication number: 20190020268
    Abstract: The switching power supply apparatus including a transformer includes a detection unit configured to detect that the power supply apparatus malfunctions and a first holding unit configured to turn off a first switching element and holds the first switching element at turn-off condition, and when the detection unit detects that malfunction occurs, the first holding unit releases the first switching element from the turn-off condition at a timing when the control unit turns on the second switching element by a second control signal.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 17, 2019
    Inventors: Yusuke Saito, Hiroki Asano, Yasuhiro Shimura
  • Storage device and method of controlling the storage device
    Patent number: 10176874
    Abstract: A storage device includes bit lines including a first bit line and a second bit line, memory units including a first memory string having memory cells connected in series, connected to the first bit line, and a second memory string having memory cells connected in series, connected to the second bit line, word lines each connected in common to a gate of a memory cell in the first string and a gate of a memory cell in the second string, and a controller configured to control voltages applied to the bit lines and the word lines during writing. When writing is performed on a selected memory cell of the first memory string, a first voltage is applied to a selected word line connected to the gate of the selected memory cell while a second voltage higher than a zero voltage is applied to the first bit line.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomohiro Kuki, Yasuhiro Shimura
  • Power source device and image forming apparatus
    Patent number: 10139770
    Abstract: A power source device includes a transformer including a primary winding and a secondary winding; a switching element for enabling or disabling supply of electric power to the primary winding by a switching operation; a controller for controlling the switching operation, wherein the controller is capable of effecting continuous control in which the switching operation is continued and intermittent control in which a switching period in which the switching operation is performed and a rest period in which the switching operation is at rest are repeated, a calculating portion not operating in the rest period; and a measuring portion continuing operation even in the rest period. When a predetermined time has elapsed from a start of the rest period, the measuring portion causes the calculating portion to resume the operation thereof, and starts the switching period.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 27, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • IMAGE FORMING APPARATUS
    Publication number: 20180335737
    Abstract: According to the present invention, a first semiconductor element to supply power to a first heat generating block out of a plurality of heat generating blocks is connected, in series, to a second semiconductor element to supply power to a second heat generating block out of a plurality of heat generating blocks. The second heat generating block is controlled by controlling the second semiconductor element, and the first heat generating block is controlled by controlling the first semiconductor element and the second semiconductor element.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 22, 2018
    Inventors: Ryota Ogura, Yuji Fujiwara, Yasuhiro Shimura