Patents by Inventor Yasuhiro Shimura

Yasuhiro Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10429781
    Abstract: In an image heating device having a plurality of heating blocks which are controllable independently in a longitudinal direction of a heater, an increase of the size of the heater can be suppressed, and temperatures of a plurality of heating block can be detected. A heater has a first temperature sensor corresponding to a first heating block, a second temperature sensor corresponding to a second heating block, a first electric conductor electrically coupled to the first temperature sensor, a second electric conductor electrically coupled to the second temperature sensor, and a common electric conductor electrically coupled to the first and second temperature sensors.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Shimura, Akira Kato, Atsushi Iwasaki
  • Patent number: 10432084
    Abstract: The switching power supply apparatus including a transformer includes a detection unit configured to detect that the power supply apparatus malfunctions and a first holding unit configured to turn off a first switching element and holds the first switching element at turn-off condition, and when the detection unit detects that malfunction occurs, the first holding unit releases the first switching element from the turn-off condition at a timing when the control unit turns on the second switching element by a second control signal.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 1, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Saito, Hiroki Asano, Yasuhiro Shimura
  • Patent number: 10416598
    Abstract: The present invention relates to an image heating apparatus that includes a heater including a plurality of independently controllable heating blocks in a longitudinal direction thereof, each including a first conductor, a second conductor, and a heating element. At least one of electrodes corresponding to the respective heating blocks is disposed in an area where the heating element is located in the longitudinal direction on a second surface of the heater that is opposite to a first surface that comes into contact with an endless belt. An electrical contact is arranged so as to face the second surface of the heater. An overheating occurring in a no-media passage portion when an image formed on a recording material having a small size is heated is suppressed or reduced.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 17, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Shimura, Koji Nihonyanagi, Ryota Ogura
  • Patent number: 10416595
    Abstract: An image forming apparatus includes a control circuit having a plurality of semiconductor elements configured to perform switching between ON and OFF of a plurality of heat generating blocks, and a power interrupting unit configured to be activated so as to interrupt power being supplied to the plurality of semiconductor elements when a heater overheats. Of the plurality of semiconductor elements, a first semiconductor element to supply power to a first heat generating block, is connected, in series, to a second semiconductor element to supply power to a second heat generating block. In addition, when the power interrupting unit is not activated, the second heat generating block is controlled by controlling only the second semiconductor element, and, when the power interrupting unit is not activated, the first heat generating block is controlled by controlling the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 17, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryota Ogura, Yuji Fujiwara, Yasuhiro Shimura
  • Publication number: 20190279716
    Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
  • Publication number: 20190260295
    Abstract: The power supply apparatus includes a control unit configured to perform control of gradually changing a turn-on duty of a first switching element when a first voltage mode is switched to a second voltage mode or when the second voltage mode is switched to the first voltage mode.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • Patent number: 10389259
    Abstract: The power supply apparatus switches the capacitance of a resonance capacitor to a first value at the time of a continuous operation, and switches the capacitance of the resonance capacitor to a second value smaller than the first value at the time of an intermittent operation.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 20, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Asano, Yasuhiro Shimura
  • Patent number: 10347338
    Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
  • Publication number: 20190198527
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Yasuhiro SHIMURA
  • Patent number: 10320299
    Abstract: The power supply apparatus includes a control unit configured to perform control of gradually changing a turn-on duty of a first switching element when a first voltage mode is switched to a second voltage mode or when the second voltage mode is switched to the first voltage mode.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 11, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • Publication number: 20190155199
    Abstract: An image forming apparatus includes a driving unit that supplies electric power to a heating element of a heater; a plurality of temperature detection portion disposed on a first potential side to detect temperatures of the heater; a control unit that is disposed on a second potential side isolated from the first potential side to control the driving unit on the basis of the temperatures detected by the temperature detection portion; a plurality of abnormality detection circuit portions disposed on the first potential side to output signals corresponding to detection results obtained by the plurality of temperature detection portion; and an abnormality transmission circuit portion that transmits an abnormality in the heater to the control unit on the basis of at least one of the signals output by the plurality of abnormality detection circuit portions.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 23, 2019
    Inventors: Yusuke Saito, Ryota Ogura, Yasuhiro Shimura
  • Publication number: 20190149054
    Abstract: The power supply apparatus includes a transformer, at least one switching element provided on a primary side of the transformer and configured to perform a switching operation to output an output voltage from a secondary side of the transformer, and a control unit configured to determine a turn-on time of a pulse signal for controlling the switching element for each of first cycles, and perform a predetermined control in which a change value of the turn-on time of the pulse signal for each of second cycles each including the first cycles becomes smaller than a change value of the turn-on time of the pulse signal for each of the first cycles, to change the second cycle depending on operation states.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 16, 2019
    Inventors: Yasuhiro Shimura, Hiroki Asano
  • Patent number: 10262703
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, a first word line electrically coupled to the first memory cell, a second word line electrically coupled to the second memory cell, and a control circuit configured to supply voltages to the first word line and the second word line. In a read, the control circuit applies a first voltage to the first word line and a second voltage to the second word line, applies, after applying the first voltage to the first word line and the second voltage to the second word line, a third voltage lower than the first voltage and the second voltage to the second word line, and applies, after applying the third voltage to the second word line, the third voltage to the first word line.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Keita Kimura
  • Patent number: 10263008
    Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Nishida, Katsuyuki Sekine, Hirokazu Ishigaki, Yasuhiro Shimura
  • Patent number: 10255979
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhiro Shimura, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
  • Publication number: 20190098159
    Abstract: The power supply apparatus includes a transformer, a switching unit provided on a primary side of the transformer and configured to perform switching operation for converting an input voltage resulting from rectification and smoothing of an AC voltage and outputting an output voltage from a secondary side of the transformer; a first detection unit configured to detect the output voltage, a feedback unit configured to generate a feedback voltage based on the voltage detected by the first detection unit; a control unit configured to control the switching operation of the switching unit based on the feedback voltage generated by the feedback unit; and a second detection unit configured to detect the AC voltage.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Inventors: Hiroki Asano, Yasuhiro Shimura
  • Patent number: 10242998
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Shimura
  • Publication number: 20190088342
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhiro SHIMURA, Shinichi Oosera, Junichi Kijima, Tomoki Higashi, Sumito Ohtsuki, Tomohiro Oda, Keisuke Yonehama
  • Publication number: 20190088663
    Abstract: A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 21, 2019
    Inventors: Go SHIKATA, Yasuhiro SHIMURA
  • Publication number: 20190058386
    Abstract: The power supply apparatus alternately repeats a control between a first control of varying a frequency of switching operation within a predetermined range and for a predetermined cycle according to a frequency determined based on a feedback voltage, and a second control of varying the frequency within a range narrower than the predetermined range or a third control of controlling the frequency to be a constant frequency.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 21, 2019
    Inventor: Yasuhiro Shimura