Patents by Inventor Yasuhiro Shimura
Yasuhiro Shimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180316269Abstract: The power supply apparatus includes a control unit configured to perform control of gradually changing a turn-on duty of a first switching element when a first voltage mode is switched to a second voltage mode or when the second voltage mode is switched to the first voltage mode.Type: ApplicationFiled: April 20, 2018Publication date: November 1, 2018Inventors: Yasuhiro Shimura, Hiroki Asano
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Patent number: 10101695Abstract: An image heating apparatus including a supporting member having (a) a hole in which a temperature detecting element is disposed so as to contact a second surface of a heat-conductive member, and (b) an opposing surface that (i) opposes the second surface of the heat-conductive member, and (ii) includes a contact region contacting the second surface of the heat-conductive member, the opposing surface of the supporting member being provided adjacent to the hole of the supporting member in a longitudinal direction of the heater. The contact region of the supporting member presses, toward the heater, a part of the heat-conductive member corresponding to the contact region of the supporting member, and the temperature detecting element presses, toward the heater, a part of the heat-conductive member corresponding to the hole of the supporting member.Type: GrantFiled: June 15, 2017Date of Patent: October 16, 2018Assignee: Canon Kabushiki KaishaInventors: Yasuhiro Shimura, Hideaki Yonekubo, Hisashi Nakahara, Akira Kato, Noriaki Tanaka, Hideyuki Matsubara, Yuji Fujiwara
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Publication number: 20180268906Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: September 8, 2017Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Tomoki HIGASHI, Sumito OHTSUKI, Junichi KIJIMA, Keisuke YONEHAMA, Shinichi OOSERA, Yuki KANAMORI, Hidehiro SHIGA, Koki UENO
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Publication number: 20180261267Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, a first word line electrically coupled to the first memory cell, a second word line electrically coupled to the second memory cell, and a control circuit configured to supply voltages to the first word line and the second word line. In a read, the control circuit applies a first voltage to the first word line and a second voltage to the second word line, applies, after applying the first voltage to the first word line and the second voltage to the second word line, a third voltage lower than the first voltage and the second voltage to the second word line, and applies, after applying the third voltage to the second word line, the third voltage to the first word line.Type: ApplicationFiled: September 12, 2017Publication date: September 13, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Keita Kimura
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Publication number: 20180253043Abstract: In an image heating device having a plurality of heating blocks which are controllable independently in a longitudinal direction of a heater, an increase of the size of the heater can be suppressed, and temperatures of a plurality of heating block can be detected. A heater has a first temperature sensor corresponding to a first heating block, a second temperature sensor corresponding to a second heating block, a first electric conductor electrically coupled to the first temperature sensor, a second electric conductor electrically coupled to the second temperature sensor, and a common electric conductor electrically coupled to the first and second temperature sensors.Type: ApplicationFiled: August 12, 2016Publication date: September 6, 2018Inventors: Yasuhiro Shimura, Akira Kato, Atsushi Iwasaki
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Patent number: 10067457Abstract: A controller controls first and second switching elements so that, in both of the waveforms of alternating currents flowing through the first and second heating elements, a first period including both of a phase control waveform in which a current flows in a part of a half cycle of alternately current and a wave-number control waveform in which a current flows or does not flow over a half cycle of alternately current and a second period including only the wave-number control waveform alternately appear in a control cycle; when the first heating element operates in the first/second period, the second heating element operates in the second/first period; and both the waveforms of the alternating currents flowing through the first and second heating elements are electrically symmetric in the positive and negative directions during the control cycle.Type: GrantFiled: May 3, 2016Date of Patent: September 4, 2018Assignee: Canon Kabushiki KaishaInventors: Yuji Fujiwara, Yasuhiro Shimura
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Patent number: 10063157Abstract: A power source device includes a transformer including a primary winding and a secondary winding; a first switch portion connected with the primary winding in series; a circuit including a capacitor and a second switch portion connected in series and connected with the primary winding in parallel; a controller for controlling conduction between the first switch portion and the second switch portion, wherein the first switch portion and the second switch portion are alternately conducted to generate an output voltage at a secondary side of the transformer, a detecting portion for detecting a current flowing through the first switch portion. The controller controls conduction of the first switch portion and the second switch portion so that a value of the current detected by the detecting portion does not exceed a threshold depending on conduction times of the first switch portion and second switch portion.Type: GrantFiled: December 15, 2016Date of Patent: August 28, 2018Assignee: CANON KABUSHIKI KAISHAInventors: Hiroki Asano, Yasuhiro Shimura
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Patent number: 10050055Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.Type: GrantFiled: April 18, 2017Date of Patent: August 14, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuhiro Shimura
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Publication number: 20180212508Abstract: The power supply apparatus, when a switching element is driven at a second frequency lower than a first frequency, determines a duty of a pulse signal according to a predetermined voltage so that a frequency of the pulse signal input to a feedback unit is equal to or more than a predetermined frequency.Type: ApplicationFiled: January 16, 2018Publication date: July 26, 2018Inventors: Junya Kobayashi, Yasuhiro Shimura, Jun Kawakatsu
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Patent number: 10032790Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; and a plate portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers include first to third electrode layers. The first electrode layer is most proximal to the substrate. The second electrode layer is most distal to the substrate. The columnar portion and the plate portion are provided inside the stacked body. The plate portion extends along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction. The plate portion includes first to third portions. The third portion is provided between the first portion and the second portion. Widths of the first portion and the second portion along a second direction are narrower than a width of the third portion along the second direction.Type: GrantFiled: September 12, 2016Date of Patent: July 24, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuhiro Shimura
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Patent number: 10027837Abstract: An apparatus includes a calculation unit configured to calculate information about power using a first signal and a second signal, a first communication unit configured to transmit a calculation result of the calculation unit, and a second communication unit configured to receive a plurality of pieces of setting information stored in a storage unit, wherein the calculation apparatus is capable of switching calculation processing of the calculation unit based on the plurality of pieces of setting information received via the second communication unit.Type: GrantFiled: October 26, 2016Date of Patent: July 17, 2018Assignee: CANON KABUSHIKI KAISHAInventors: Yasuhiro Shimura, Tatsuya Hotogi, Yuki Nakajima
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Patent number: 9978769Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; a plate portion; and a sidewall insulating film. The thermal expansion coefficient of the substrate is ?1. The stacked body includes a plurality of electrode layers and a memory cell array. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a first layer and a second layer. The thermal expansion coefficient of the first layer is the ?2 being different from the ?1. The thermal expansion coefficient of the second layer is the ?3 being different from the ?2. The value of the ?3 is in a direction from the value of the ?2 toward the value of the ?1. The second layer faces the major surface of the substrate continuously in the memory cell array.Type: GrantFiled: March 10, 2016Date of Patent: May 22, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuhiro Shimura
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Patent number: 9966865Abstract: The power supply apparatus includes a control unit that can perform intermittent operation of alternately repeating a switching period and a switching halt period, wherein the switching period is for performing switching operation of alternately turning on or turning off two switching elements across a turn-off period for turning off both of the two switching elements, and the switching halt period is for halting the switching operation. In a transition from the switching period to the switching halt period, the control unit makes the transition to the switching halt period after turning on a second switching element. In a transition from the switching halt period to the switching period, the control unit also makes the transition to the switching period after turning on the second switching element.Type: GrantFiled: June 6, 2016Date of Patent: May 8, 2018Assignee: CANON KABUSHIKI KAISHAInventors: Yasuhiro Shimura, Hiroki Asano
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Patent number: 9897964Abstract: The power supply apparatus includes first line and lines to each of which an AC voltage is input, a first capacitor arranged between the first and secondary lines, a voltage detection unit configured to detect the AC voltage, a conversion element to be connected to the first line or the secondary line, the conversion element being configured to convert the AC voltage to be input to the first line or the secondary line into a current corresponding to the AC voltage, a switch configured to switch between connection and disconnection of the voltage detection unit and the conversion element, and a control unit configured to control the voltage detection unit and the switch.Type: GrantFiled: August 29, 2016Date of Patent: February 20, 2018Assignee: Canon Kabushiki KaishaInventor: Yasuhiro Shimura
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Patent number: 9823617Abstract: The power supply apparatus includes a first line and a second line to each of which an AC voltage is input from an AC power supply; a conversion element configured to convert the AC voltage to be input to the first line or the second line into a current corresponding to the AC voltage; a voltage detection unit including a first current transformer, the first current transformer including a primary winding and a secondary winding, the voltage detection unit being configured to detect an AC voltage output from the secondary winding of the first current transformer through supply of the current converted by the conversion element to the primary winding; and a zero cross detection unit configured to detect a zero cross timing of the AC power supply based on the AC voltage detected by the voltage detection unit.Type: GrantFiled: September 16, 2016Date of Patent: November 21, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Yasuhiro Shimura, Masatoshi Itoh
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Patent number: 9805808Abstract: According to one embodiment, a semiconductor device includes a memory cell array, word lines, bit lines, a source line, and a circuit controlling a read operation of the information. The memory cell array includes a plurality of memory strings. The plurality of memory strings includes a plurality of memory cells connected in series. The plurality of memory cells connected to one of the word lines is included in a unit of a page. Each bit line is connected to one end of the plurality of memory strings. The source line is connected to one other end of the plurality of memory strings. The circuit applies a pre-charge voltage to the plurality of bit lines in the read operation and changes the pre-charge voltage according to at least one of a number of used pages, a position of the page, or a number of programmed memory cells.Type: GrantFiled: July 1, 2016Date of Patent: October 31, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuhiro Shimura
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Publication number: 20170285543Abstract: An image heating apparatus includes: a heater including a substrate and a heat generating element; a supporting member; a high heat-conductive member. The recording material on which an image is formed is heated by heat from the heater. The supporting member has a bottom region, where the supporting member supports the heater, including a first region where the supporting member contacts the high heat-conductive member so as to apply pressure between the heater and the high heat-conductive member and including a second region where the supporting member is recessed from the high heat-conductive member relative to the first region. At least a part of the first region overlaps, with respect to a movement direction of the recording material, with a region where the heat generating element is provided.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Inventors: Yasuhiro Shimura, Hideaki Yonekubo, Hisashi Nakahara, Akira Kato, Noriaki Tanaka, Hideyuki Matsubara, Yuji Fujiwara
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Patent number: 9772586Abstract: An image heating device includes, a moving member configured to move while contacting a recording material at one surface of the moving member, a backup member configured to contact the other surface of the moving member, a holding member configured to hold the backup member, a nip portion forming member contacting the one surface of the moving member, and configured to form a nip portion in corporation with the backup member via the moving member, and a high thermal conductive member held between the holding member and the backup member, wherein the recording material on which an image has been formed is heated by heat received from the moving member while being nipped and conveyed at the nip portion, and wherein the holding member includes a recessed portion configured not to apply pressure to the high thermal conductive member.Type: GrantFiled: November 25, 2014Date of Patent: September 26, 2017Assignee: Canon Kabushiki KaishaInventors: Hideyuki Matsubara, Hideaki Yonekubo, Hisashi Nakahara, Akira Kato, Noriaki Tanaka, Yasuhiro Shimura, Yuji Fujiwara
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Publication number: 20170271000Abstract: The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second threshold voltage distribution lower than the first threshold voltage distribution, and a third threshold voltage distribution higher than the first threshold voltage distribution. A verify reading operation is performed to determine whether any of the first to third threshold voltage distributions has been obtained. A step-up writing operation, in accordance with a result of the verify reading operation, increases a program voltage by a predetermined step-up width. The step-up writing operation, after start of the second writing operation, sets the step-up width to a first step-up width, and when the second writing operation has reached a predetermined phase, changes a second step-up width greater than the first step-up width at least once.Type: ApplicationFiled: September 16, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: YASUHIRO SHIMURA
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Publication number: 20170271345Abstract: According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.Type: ApplicationFiled: August 4, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasuhiro SHIMURA
