Patents by Inventor Yasuhiro Sugawara

Yasuhiro Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347724
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Katsutoshi Sugawara, Yasuhiro Kagawa, Naruhisa Miura
  • Publication number: 20190179517
    Abstract: A screen generating unit generates a home screen for allowing a user to select a desired item of content from among multiple items of content, and the home screen includes a list in which multiple icons representing the multiple items of content are arranged. A display control unit displays the home screen on a television monitor. The screen generating unit further arranges, in the list on the home screen, a search icon used to search for an item of content.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Applicant: c/o Sony Interactive Entertainment Inc.
    Inventors: Motoki KOBAYASHI, Yasuhiro YAMANAKA, Shuji HIRAMATSU, Shigeru ENOMOTO, Taku SUGAWARA, Shinji KIMURA, Yumiko TANAKA, George ARRIOLA, Carsten SCHWESIG
  • Patent number: 10318124
    Abstract: A screen generating unit 287 generates a home screen for allowing a user to select a desired item of content from among multiple items of content, and the home screen includes a list in which multiple icons representing the multiple items of content are arranged. A display control unit displays the home screen on a television monitor 204. The screen generating unit 287 further arranges, in the list on the home screen, a search icon used to search for an item of content.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: June 11, 2019
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Motoki Kobayashi, Yasuhiro Yamanaka, Shuji Hiramatsu, Shigeru Enomoto, Taku Sugawara, Shinji Kimura, Yumiko Tanaka, George Arriola, Carsten Schwesig
  • Patent number: 10312233
    Abstract: A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 4, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsutoshi Sugawara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Patent number: 10178977
    Abstract: According to an embodiment, a grid is provided between an X-ray generator and a flat panel detector. Processing circuitry configured to convert original image based on X-rays having passed through the grid and detected into a plurality of pieces of frequency band data, remove interference fringes contained in at least one piece of frequency band data among the pieces of frequency band data, reduce noise contained in the pieces of frequency band data, correct a scattered radiation of the original image based on a scattered radiation contained in the X-rays having passed through the grid and a scattered radiation contained in X-rays having passed through a grid that removes scattered radiation to a larger extent than the grid, and synthesize a plurality of pieces of frequency band data to generate image.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 15, 2019
    Assignee: Toshiba Medical Systems Corporation
    Inventors: Hisanori Kato, Yasuhiro Sugawara, Yoshimasa Kobayashi
  • Patent number: 9978163
    Abstract: An exposure management system according to an embodiment includes a processing circuitry. The processing circuitry is configured to calculate a deviation index related to a difference between a target exposure index indicating an index of an exposure value that is set as a target of an X-ray image taking process and an image-taking-period exposure index indicating an index of an exposure value observed during the X-ray image taking process. The processing circuitry is configured to control so as to cause a display device to display history information from a predetermined time period indicating at least one selected from between image-taking-period exposure indices and deviation indices.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: May 22, 2018
    Assignee: Toshiba Medical Systems Corporation
    Inventors: Seiichirou Nagai, Yasuhiro Sugawara, Atsushi Kotani, Tsutomu Ichikawa, Toshikatsu Oohashi, Shoji Yashiro
  • Publication number: 20160021727
    Abstract: An exposure management system according to an embodiment includes a processing circuitry. The processing circuitry is configured to calculate a deviation index related to a difference between a target exposure index indicating an index of an exposure value that is set as a target of an X-ray image taking process and an image-taking-period exposure index indicating an index of an exposure value observed during the X-ray image taking process. The processing circuitry is configured to control so as to cause a display device to display history information from a predetermined time period indicating at least one selected from between image-taking-period exposure indices and deviation indices.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 21, 2016
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventors: Seiichirou NAGAI, Yasuhiro SUGAWARA, Atsushi KOTANI, Tsutomu ICHIKAWA, Toshikatsu OOHASHI, Shoji YASHIRO
  • Publication number: 20150317771
    Abstract: According to an embodiment, a grid is provided between an X-ray generator and a flat panel detector. Processing circuitry configured to convert original image based on X-rays having passed through the grid and detected into a plurality of pieces of frequency band data, remove interference fringes contained in at least one piece of frequency band data among the pieces of frequency band data, reduce noise contained in the pieces of frequency band data, correct a scattered radiation of the original image based on a scattered radiation contained in the X-rays having passed through the grid and a scattered radiation contained in X-rays having passed through a grid that removes scattered radiation to a larger extent than the grid, and synthesize a plurality of pieces of frequency band data to generate image.
    Type: Application
    Filed: April 24, 2015
    Publication date: November 5, 2015
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Medical Systems Corporation
    Inventors: Hisanori KATO, Yasuhiro Sugawara, Yoshimasa Kobayashi
  • Publication number: 20140193082
    Abstract: According to one embodiment, an image processing apparatus includes following units. The selection unit selects a pixel from a target image. The first extraction unit extracts a first pixel region including the selected pixel. The second extraction unit extracts a second pixel region from a reference image. The determination unit determines a filter coefficient based on a similarity degree between the first and second pixel regions. The generation unit generates a display image by performing a weighted sum of the target image and a display image generated immediately before the target image, in accordance with the filter coefficient determined for each of the plurality of pixels of the target image.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicants: Toshiba Medical Systems Corporation, KABUSHIKI KAISHA TOSHIBA
    Inventors: Kae OHNUKI, Hisanori KATO, Yasuhiro SUGAWARA
  • Patent number: 8351346
    Abstract: A communication device capable of improving power saving is provided. A communication device (1) includes a communication port (10); communication monitoring sections (18, 22) for controlling information communication using the communication port, a status indicating section (12) having one or more status indicators, a status indicator driving section (20) for controlling a drive signal which detects a communication status from the communication monitoring sections and is supplied to the status indicating section on the basis of the communication status, and a lighting control section (24) for detecting the communication status from the communication monitoring sections and outputting a control signal to the status indicator driving section if the communication status changes from a first status to a second status. The status indicator driving section controls the drive signal so as to turn off the status indicators when the control signal is outputted from the lighting control section.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 8, 2013
    Assignee: Allied Telesis Holdings K.K.
    Inventors: Seiho Itano, Yasuhiro Sugawara
  • Publication number: 20100260058
    Abstract: A communication device capable of improving power saving is provided. A communication device (1) includes a communication port (10); communication monitoring sections (18, 22) for controlling information communication using the communication port, a status indicating section (12) having one or more status indicators, a status indicator driving section (20) for controlling a drive signal which detects a communication status from the communication monitoring sections and is supplied to the status indicating section on the basis of the communication status, and a lighting control section (24) for detecting the communication status from the communication monitoring sections and outputting a control signal to the status indicator driving section if the communication status changes from a first status to a second status. The status indicator driving section controls the drive signal so as to turn off the status indicators when the control signal is outputted from the lighting control section.
    Type: Application
    Filed: October 20, 2008
    Publication date: October 14, 2010
    Applicant: ALLIED TELESIS HOLDINGS K.K.
    Inventors: Seiho Itano, Yasuhiro Sugawara
  • Patent number: 6724855
    Abstract: An X-ray flat panel detector includes sensor elements constituted by a plurality of effective pixels that detect X-rays and a plurality of dummy pixels that are arranged adjacent to the effective pixel area and generate electrical signals irrelevant to X-rays, signal lines which read out electrical signals from the respective pixels, scanning lines which scan the respective pixels, a first electrostatic wiring line which distributes static electricity accumulated in the signal lines, and a second electrostatic wiring line which distributes static electricity accumulated in the scanning lines. A plurality of dummy pixels are classified into a DA area where noise superposed on the signal lines are removed and a DB area where noise superposed on the scanning lines are removed. The first and second electrostatic wiring lines are laid out around the sensor elements, and physically disconnected between the DA area and the DB area.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: April 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Sugawara, Takayuki Tomisaki, Manabu Tanaka, Akira Tsukamoto
  • Patent number: 6717202
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 6, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
  • Patent number: 6713343
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai, Masahiko Hiratani
  • Patent number: 6627497
    Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: September 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Naruhiko Nakanishi, Nobuyoshi Kobayashi, Yuzuru Ohji, Sinpei Iijima, Yasuhiro Sugawara, Misuzu Kanai
  • Publication number: 20030162357
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Application
    Filed: March 17, 2003
    Publication date: August 28, 2003
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai
  • Patent number: 6583463
    Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: June 24, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Naruhiko Nakanishi, Nobuyoshi Kobayashi, Yuzuru Ohji, Sinpei Iijima, Yasuhiro Sugawara, Misuzu Kanai
  • Patent number: 6576946
    Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Misuzu Kanai, Yuzuru Ohji, Takuya Fukuda, Shinpei Iijima, Ryouichi Furukawa, Yasuhiro Sugawara, Hideharu Yahata
  • Patent number: 6544834
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai, Masahiko Hiratani
  • Publication number: 20030038325
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Application
    Filed: October 17, 2002
    Publication date: February 27, 2003
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iijima, Yuzuru Ohji