Abstract: An analog-digital converter comprises a first comparing-converting device for comparing analog input voltages and a plurality of primary reference voltages at different levels, respectively, and converting the analog input voltages to digital signals on the most significant bit sides; a reference voltage generating device for generating a plurality of secondary reference voltages at different levels from the primary reference voltages supplied to both terminals of the reference voltage generating device; a switching device for supplying the primary reference voltage most close in sequential order to the analog input voltages to the reference voltage generating device in accordance with the compared results of the first comparing-converting device; a second comparing-converting device for converting the compared results between the analog input voltages and the secondary reference voltages to signals corresponding to digital signals on the least significant bit side with respect to the analog input voltages; a

Abstract: An input circuit is disclosed, which can be driven by a single power supply, and which can convert an ECL-level input signal falling to a negative voltage into a CMOS-level signal rising to a positive voltage, and can then supply this CMOS-level signal to an inner circuit. The input circuit comprises a transistor, a bias circuit, and a current-to-voltage converter. The emitter of the transistor is coupled to an input terminal for receiving a signal of a negative potential. The bias circuit applies a negative bias voltage to the base of the transistor. The current-to-voltage converter is connected to the collector of the transistor. The converter outputs a signal which first falls to a positive level and then rises to another positive level. That is, the input circuit can convert an input signal of a negative level to a signal of a positive level.

Abstract: A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

Abstract: In the output circuit a signal from an internal circuit is supplied to the gate of an N-channel type MOS transistor, a node of two resistors connected in series across a power supply terminal and ground is connected to one end of the MOS transistor. An NPN transistor is connected at its base to the node, at its collector to the power supply terminal and at its emitter to an output terminal. The positive polarity terminal of a power supply is connected to the power supply terminal to supply a positive voltage V.sub.CC and the negative polarity terminal of another power supply is connected through a load resistor to the output terminal to supply a negative voltage.

Abstract: Level conversion circuit for converting CMOS logic level signals to ECL logic level signals.

Abstract: Level conversion circuit for converting ECL logic level signals to CMOS logic level signals.

Abstract: A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

Abstract: Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.

Abstract: A tri-state buffer circuit according to the present invention comprises a switching circuit connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have a first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal; an inverter circuit connected to said switching circuit, and the first power supply terminal for inverting the first switching signal (A) from said switching circuit as an output signal; a selection circuit connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; a first type bipolar transistor whose base is connected to said inverter circuit, whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of t

Abstract: An improved inverter circuit capable of attaining complete swift inversion is shown. The circuit comprises bipolar transistors (27, 29) by which an inverted output takes a level near the rated level and MOS transistors (21, 23) by which the inverted output reaches the rated level from the near level. The MOS transistor (21, 23) is driven by a bipolar transistor (31) and possesses high current driving capacity with its large dimensions of the gate region.

Abstract: A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit.

Abstract: This invention provides a level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to the input terminal; a first MOS transistor of a first channel type, the source of which is connected to the second power supply, and the gate of which is connected to the output of the inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of the first MOS transistor to voltage change, a first terminal of which is connected to the drain of the first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of the second channel type, the source of which is connected to the third power supply, and the gate of which is connected to the first terminal of the current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is

Abstract: A voltage level converting circuit includes first and second potential terminals between which a power source voltage is applied, first and second terminals for receiving an input signal and an inverted input signal, a differential amplifier including npn transistors whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier. The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals by way of a constant current source, and includes a MOS transistor whose conduction state is controlled by the output voltage of the differential amplifier.

Abstract: An outboard engine has a power unit, an extension case extending vertically and having its upper end coupled to the power unit, and a propeller mounted on the lower end of the extension case and driven by the power unit. The power unit comprises an internal combustion engine having a vertically extending crank shaft and a cylinder having its axis extending horizontally, and a cover assembly covering the internal combustion engine. The axis of the cylinder is inclined to one side with respect to the axis of the propeller when viewed in plan. The outboard engine can be handled with utmost ease since it can be laid down during storage or shipment without being drained of engine oil.

Abstract: The sample and hold circuit includes a capacitor and first NPN and PNP transistors for respectively controlling the charge and discharge of the capacitor. The first NPN and PNP transistors are fed with base currents from the second PNP and NPN transistors. The sample and hold circuit further includes a driving controller. The driving controller periodically bypasses the base currents of the first NPN and PNP transistors.

Abstract: In a disclosed amplifier circuit, P channel MOS transistors, as input elements, are connected at the sources to the emitters of bipolar transistors.

Abstract: A differential amplifier has first and second transistors whose bases respectively receive first and second voltage signals. The collectors of the first and second npn transistors are commonly connected to a power source terminal respectively through resistors. The emitters of the first and second npn transistors are grounded through a constant current source. The differential amplifier further has first and second pnp transistors in a common-base configuration. The collectors of the first and second npn transistors are connected to the emitters of the first and second pnp transistors.

Abstract: A quantizer-subtractor circuit is provided with a input circuit for inputting an input signal and a circuit for producing a digital signal corresponding to the input signal. The quantizer-subtractor circuit contains 2.sup.n transistors. These transistors are supplied with different bias voltages by a bias circuit. A control circuit is connected to the transistors and the input circuit and controls the currents passing through the 2.sup.n transistors. A circuit produces as a subtraction output a signal corresponding to the difference between the controlled currents passing through the transistors applied with the bias voltages having odd-ordered magnitudes and the currents flowing through the transistors applied having bias voltages with the even-ordered magnitudes.

Abstract: A decoder for a D/A converter comprises at least two resistor circuits, two transistor circuits, three constant current sources and a plurality of switches where the plurality of switches respond to a digital input to connect certain of the constant current sources to certain of the resistors.

Abstract: A gamma correction circuit to adjust the output of a video signal to the particular picture tube used including an exponential impedance changing element for gamma-correcting a non-gamma corrected input signal to produce a gamma-corrected signal. A current adder circuit adds the gamma-corrected signal to the non-gamma corrected input signal and includes a double balance type adder coupled to a series arrangement of variable and fixed DC voltage sources. The adder circuit has a combination of resistance means to add the gamma-corrected signal to the non-gamma corrected input signal at the desired adding ratio, while maintaining the signal levels of the gamma-corrected signal and the non-gamma corrected input signal coincident.