Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks.

Abstract: A feeding device according to the present invention includes a box, paper holders, and a shifting mechanism. The box is open at its top. The paper holders are open at their tops and positioned in the box. Each of the paper holders holds a pile of sheets of paper in it. The shifting mechanism so shifts at least one of the paper holders that the top sheet in one of the paper holders is positioned in a single feed position in the box according to selection data output from the apparatus with which the feeding device is used.

Abstract: A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

Abstract: An image forming apparatus comprising: a main body having an image forming section; a sheet feed section having a sheet cassette that accommodates a recording sheet and can be drawn out and loaded to the main body; and a sheet misalignment preventing mechanism that intermittently comes into contact with an uppermost recording sheet in the sheet cassette so as to prevent misalignment of the recording sheet in a loading direction when the sheet cassette drawn out of the main body is reloaded.

Abstract: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command.

Abstract: An image forming apparatus includes a feeding portion, an image forming portion, a discharge portion, a paper transport path, a plurality of detection members, and a control portion. The image forming portion forms images on sheets of paper fed from the feeding portion. The path transports paper from the feeding portion to the discharge portion via the image forming portion. The detection members detect transport state of paper at respective locations on the path including the feeding portion, between the feeding and image forming portions, within the image forming portion, between the image forming and discharge portions, and the discharge portion. Upon detection of paper jam at any of the locations, the control portion displays, on an indicator, information identifying a location where the jam has occurred, and the image forming portion where paper is detected by the detection members, as locations of paper to be eliminated from the path.

Abstract: A sheet feeder has a feed passage and includes feed roller pairs, sensors, and a controller. The feed roller pairs are arranged along the feed passage and feed sheets of paper in a feed direction along the passage by nipping the sheets. Each of the sensors is fitted at or near one of the feed roller pairs and senses a specified point on each of the sheets when the sheet is nipped by at least the associated roller pair. The controller includes a memory for storing reference feed timings as proper feed timings at each of which the specified points on the sheets should pass one of the sensors. The controller finds the real feed timing when each of the sensors senses the specified point on the sheet nipped by at least the associated roller pair.

Abstract: A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.

Abstract: In one embodiment, a predetermined period different from a fixing process period in which fixing of toner to recording paper is carried out is set as a toner removal period, and during the toner removal period a hot roller and a pressure roller are intermittently rotated, and separation claws in contact with the rollers are caused to vibrate by the intermittent rotation of the rollers such that toner adhered to the separation claws is caused to drop due to this and is removed. Also, faces of the separation claws that oppose the surfaces of the hot roller and the pressure roller are set in a convex shape.

Abstract: A toner supply device including: a toner bottle filled with toner; and a toner supply assembly mounting mechanism having the toner bottle mounted thereon and feeding toner discharged from the toner bottle to a developing unit and supplying toner to the developing unit in accordance with the amount of toner consumed in the developing unit for the process of printing, further comprises: a toner bottle releasing mechanism which, when the amount of toner left in the toner bottle has been reduced to a predetermined level or lower, causes the toner bottle to move in the direction opposite to the direction in which the toner bottle is set into the toner supply assembly mounting mechanism and separate from the toner feed device.

Abstract: Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1.

Abstract: A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

Abstract: One embodiment of the present invention involves a roller drive control method for a fixing apparatus in which a separation claw for separating a recording paper and a cleaning unit for removing toner that has become residual on a surface of a heat roller are arranged near a surface of the heat roller that fixes toner onto the recording paper, wherein a predetermined period different from a fixing process period in which fixing of toner onto the recording paper is carried out is set as a toner removal period for removing toner that has adhered to the separation claw, and the heat roller is rotationally driven so that the rotation velocity of the heat roller is different in the fixing process period and the toner removal period.

Abstract: In an image forming apparatus of the present invention, an idle roller once stops rotating when a front edge of a sheet conveyed reaches the idle roller. The idle roller restarts rotating at such a timing that a front edge of a toner image on a photoreceptor and a front edge of an image writing position on the sheet are aligned with each other. Then, even if a rear edge of the sheet is still in the idle roller, the idle roller stops rotating when the front edge of the sheet is sandwiched between a transfer roller and the photoreceptor. By carrying out such operations, it is possible to avoid by a very simple way an occurrence of a slip phenomenon that is a phenomenon of slipping of the sheet with respect to the photoreceptor while suppressing a reduction in image quality as much as possible. In addition, it is also possible to surely secure a blank space formed at a rear edge portion of the sheet.

Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

Abstract: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

Abstract: A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

Abstract: Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first address, generated responsive to a refresh command, with an input control signal being of a first value, a second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the information ore-programmed in a refresh redundant ROM, the cell of the second address is refreshed, and also in such a manner that, if, with the input control signal of a second value, the second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the predetermined information, only the cell of the second address is refreshed, without refreshing the cell of the first address, generated responsive to the refresh comma

Abstract: A paper feeder includes a storage section, a feed path, a delivery section, and a receiving section. The storage section is configured to store therein plural sheet members to be fed to a processing apparatus which is operative to perform processing on the sheet members. The feed path allows each of the plural sheet members fed from the storage section to pass therethrough in a feed direction toward the processing apparatus. The delivery section is located most downstream on the feed path in the feed direction. The feed path is open to exterior in the delivery section. The receiving section is located upstream of the feed path in the feed direction for communication with a delivery section of a separate paper feeder having an identical construction with the present paper feeder when the separate paper feeder is disposed upstream of the present paper feeder in the feed direction.

Abstract: In one embodiment of the invention, in an image forming apparatus that reverses the front and back of recording paper by performing switchback transport of the recording paper to perform duplex printing of the recording paper, the image forming apparatus is provided with a control means that, when performing duplex printing of the recording paper, forms a void area at a leading end and a trailing end of the recording paper, the void area preventing curling of the recording paper around a roller.