Patents by Inventor Yasuhito Aruga

Yasuhito Aruga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11668984
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: June 6, 2023
    Assignee: Japan Display Inc.
    Inventors: Hideaki Abe, Yasuhito Aruga, Hiroyuki Onodera, Hiroki Kato, Yasushi Nakano, Hitoshi Kawaguchi, Keisuke Asada
  • Publication number: 20220229324
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: Japan Display Inc.
    Inventors: Hideaki ABE, Yasuhito ARUGA, Hiroyuki ONODERA, Hiroki KATO, Yasushi NAKANO, Hitoshi KAWAGUCHI, Keisuke ASADA
  • Patent number: 11327373
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals is the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 10, 2022
    Assignee: Japan Display Inc.
    Inventors: Hideaki Abe, Yasuhito Aruga, Hiroyuki Onodera, Hiroki Kato, Yasushi Nakano, Hitoshi Kawaguchi, Keisuke Asada
  • Publication number: 20210157192
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals is the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Applicant: Japan Display Inc.
    Inventors: Hideaki ABE, Yasuhito ARUGA, Hiroyuki ONODERA, Hiroki KATO, Yasushi NAKANO, Hitoshi KAWAGUCHI, Keisuke ASADA
  • Patent number: 10921657
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 16, 2021
    Assignee: Japan Display Inc.
    Inventors: Hideaki Abe, Yasuhito Aruga, Hiroyuki Onodera, Hiroki Kato, Yasushi Nakano, Hitoshi Kawaguchi, Keisuke Asada
  • Publication number: 20190250447
    Abstract: A display device includes: a display panel including panel terminals; and a wiring substrate including first substrate terminals coupled to the panel terminals. The panel terminals include panel terminals arranged in a first region and panel terminals arranged in second regions sandwiching the first region. The first substrate terminals include first substrate terminals arranged in a third region and first substrate terminals arranged in fourth regions sandwiching the third region. A gap between panel terminals is substantially constant in the first and second regions. A first width of the panel terminals in the first region is different from a second width of the panel terminals in the second regions. A width of the first substrate terminals is substantially constant in the third and fourth regions. A first gap between first substrate terminals in the third region is different from a second gap between first substrate terminals in the fourth regions.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 15, 2019
    Applicant: Japan Display Inc.
    Inventors: Hideaki ABE, Yasuhito ARUGA, Hiroyuki ONODERA, Hiroki KATO, Yasushi NAKANO, Hitoshi KAWAGUCHI, Keisuke ASADA
  • Patent number: 10288959
    Abstract: A terminal structure that keeps the resistance of its connecting portion small and secures mechanical reliability is to be achieved. A display device includes a display region and a terminal region. A terminal formed in the terminal region is formed with a terminal metal, a first oxide conductive film covering the end portion of the terminal metal, and a second oxide conductive film covering the first oxide conductive film and the terminal metal. The first oxide conductive film has an opening in the center part of the terminal.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventors: Motoharu Miyamoto, Hidetatsu Nakamura, Yasuhiro Kanaya, Yasushi Nakano, Yasuhito Aruga
  • Publication number: 20190051593
    Abstract: According to one embodiment, a display device includes a first signal wiring disposed on an insulating substrate, a base substrate, a first connection wiring on the base substrate and a conductive adhesive member which electrically connects the first signal wiring and the first connection wiring, wherein the base substrate includes a first end surface overlapping the first signal wiring, the insulating substrate includes a second end surface overlapping the first connection wiring, the first connection wiring has a first width in a position overlapping the first end surface and a second width in a position overlapping the second end surface, and the first width is less than the second width.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 14, 2019
    Inventors: Hiroyuki Kimura, Yasuhito Aruga, Hideaki Abe, Hitoshi Kawaguchi
  • Publication number: 20180046012
    Abstract: A terminal structure that keeps the resistance of its connecting portion small and secures mechanical reliability is to be achieved. A display device includes a display region and a terminal region. A terminal formed in the terminal region is formed with a terminal metal, a first oxide conductive film covering the end portion of the terminal metal, and a second oxide conductive film covering the first oxide conductive film and the terminal metal. The first oxide conductive film has an opening in the center part of the terminal.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 15, 2018
    Inventors: Motoharu MIYAMOTO, Hidetatsu NAKAMURA, Yasuhiro KANAYA, Yasushi NAKANO, Yasuhito ARUGA
  • Patent number: 7888799
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: February 15, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Publication number: 20100252829
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Application
    Filed: May 10, 2010
    Publication date: October 7, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuichi TANAKA, Haruki ITO, Yasuhito ARUGA, Ryohei TAMURA, Michiyoshi TAKANO
  • Patent number: 7741712
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 22, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Patent number: 7567330
    Abstract: An electro-optical device includes a substrate having a display region; and an extending region extending from the display region. The extending region is provided with wiring lines, and at least some wiring lines, which are disposed to be adjacent to each other, are correspondingly disposed in a plurality of different layers.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 28, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Kazuyuki Yamada, Yasuhito Aruga
  • Publication number: 20080272471
    Abstract: An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected to the input bumps that are positioned substantially at the center of the semiconductor device in the first direction have allowable connection resistance values smaller than those of the other input terminals.
    Type: Application
    Filed: June 25, 2008
    Publication date: November 6, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki ONODERA, Yasuhito ARUGA
  • Publication number: 20080012130
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Application
    Filed: September 14, 2007
    Publication date: January 17, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuichi TANAKA, Haruki ITO, Yasuhito ARUGA, Ryohei TAMURA, Michiyoshi TAKANO
  • Patent number: 7276792
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: October 2, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Patent number: 7167227
    Abstract: A liquid crystal device comprises a pair of substrates 2a and 2b, liquid crystal L held between the substrates 2a and 2b, and an IC 13 mounted on an overhang section 2c of the substrate 2a. A terminal column 26a comprises a plurality of terminals 18 aligned in a direction away from the liquid crystal L. The terminal column 26a has, in the order of the closeness to the liquid crystal L, a first noneffective terminal region within a distance “A” from a first side of the IC, an effective terminal region X continuing from the first noneffective terminal region, and a second noneffective terminal region within a distance “B” from a second side of the IC, the second noneffective terminal region continuing from the effective terminal region. The distances A and B are adjusted to satisfy the relationship A>B.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: January 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Yasuhito Aruga, Ryosuke Imaseki
  • Patent number: 7148427
    Abstract: A wiring substrate is formed of a plurality of metal wirings 14e formed on a substrate 7c. A guard wiring 29 fabricated of an electrically conductive oxide such as ITO is interposed between at least a pair of adjacent ones of a plurality of metal wirings 14e. When voltages V1, V2, V3, and V4 applied to the metal wirings 14e are related to be V1>V2>V3>V4, a guard wiring 29 is present between a metal wiring 14e functioning as an anode and a metal wiring 14e functioning as a cathode, and the anode metal wiring 14e is prevented from being corroded.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: December 12, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yasuhito Aruga, Satoshi Yatabe, Kogo Endo, Norihito Harada
  • Patent number: 7119801
    Abstract: A display device includes a display panel having an electrooptic material provided between a pair of substrates opposed to each other. The display panel has a driver integrated circuit mounted on an extended area in which an edge of one of the substrates extends further than an edge of the other substrate. The extended area is provided in at least a margin of the display panel. A control circuit board is provided above the driver integrated circuit almost within the extended area. The control circuit board is connected to the input terminal portion of the driver integrated circuit.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: October 10, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Kogo Endo, Eiji Oishi, Yasuhito Aruga
  • Publication number: 20060076656
    Abstract: An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected to the input bumps that are positioned substantially at the center of the semiconductor device in the first direction have allowable connection resistance values smaller than those of the other input terminals.
    Type: Application
    Filed: September 13, 2005
    Publication date: April 13, 2006
    Inventors: Hiroyuki Onodera, Yasuhito Aruga