Abstract: In one embodiment, a semiconductor integrated circuit is provided a first well region, a second well region, a first body bias supply unit and a second body bias supply unit. The first well region includes a first transistor having a first threshold voltage. The second well region includes a second transistor having an absolute value of a second threshold voltage higher than an absolute value of the first threshold voltage. The second well region is separated from the first well region. The second well region has the same conductive type as the first well region. The first body bias supply unit supplies a first body bias voltage to the first well region. The second body bias supply unit supplies a second body bias voltage to the second well region.

Abstract: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.

Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Abstract: Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.

Abstract: A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether or not the voltage drop value exceeds a threshold value for each node, and inserts a buffer to a node determined that the voltage drop value exceeds the threshold value.

Abstract: A method of designing a semiconductor integrated circuit, comprises: replacing a circuit element disposed in the semiconductor integrated circuit with a transistor having a high threshold value or a circuit element having a small juxtaposition number in order to prevent deviation of a signal voltage flowing through the semiconductor integrated circuit from a power voltage and a ground voltage; replacing a circuit element disposed in a subsequent stage of the replaced circuit element in order to prevent the deviation of the signal voltage from the power voltage and the ground voltage from being propagated to a subsequent stage with a transistor having a high threshold value or a circuit element having a small juxtaposition number; and then arranging circuit elements constituting the semiconductor integrated circuit in such a manner that the semiconductor integrated circuit stably operates.

Abstract: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Abstract: A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether or not the voltage drop value exceeds a threshold value for each node, and inserts a buffer to a node determined that the voltage drop value exceeds the threshold value.

Abstract: In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

Abstract: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.

Abstract: A method of designing a semiconductor integrated circuit, comprises: replacing a circuit element disposed in the semiconductor integrated circuit with a transistor having a high threshold value or a circuit element having a small juxtaposition number in order to prevent deviation of a signal voltage flowing through the semiconductor integrated circuit from a power voltage and a ground voltage; replacing a circuit element disposed in a subsequent stage of the replaced circuit element in order to prevent the deviation of the signal voltage from the power voltage and the ground voltage from being propagated to a subsequent stage with a transistor having a high threshold value or a circuit element having a small juxtaposition number; and then arranging circuit elements constituting the semiconductor integrated circuit in such a manner that the semiconductor integrated circuit stably operates.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.

Abstract: There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.

Abstract: In a standard cell, rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level voltage differ from each other. A flip-flop outputs a first input signal, which is input in a cycle immediately before a clock in synchronization with one of rise and fall of the clock, to the standard cell and then fixes an output the signal at one of a high-level voltage and a low-level voltage. Before a second input signal, which is output from the flip-flop after the first input signal, reaches the standard cell, an output of the standard cell is set at one of a high-level voltage and a low-level voltage, which corresponds to a signal whose transition speed is slow, by one of the high-level voltage and the low-level voltage that is output from the flip-flop.

Abstract: A semiconductor integrated circuit is disclosed, which comprises a pre-charge type dynamic circuit, a static circuit which realizes the same logic as the dynamic circuit, a selection circuit which is connected to an input section of each of the dynamic circuit and the static circuit, a control circuit which controls the selection circuit to select either the dynamic circuit or the static circuit at the time of testing a semiconductor chip.